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100 Gbit/s IEEE 802.3bj RS Encoder/ Decoder

The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.

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100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. 

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100G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 100G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra-low Latency.

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10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. 

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10G/25G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

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10M/100M/1G/10G/25G High capacity Ethernet TSN Switch

The 10M/100M/1G/10G/25G/100G Ethernet Switching IP is an advanced Ethernet Switch IP with an extensive set of QoS features, statistics and Time Sensitive Networking (TSN) capabilities.

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1G-100G Robo/TSN Industrial Network Virtualization and Acceleration for Converged OT/IT - MLE FPGA Design Services

Openness has greatly benefited other industries like automotive, aerospace, banking, datacenters, and finally OT: No vendor lock-in, higher flexibility and better long-term-availability. Cost reduction for Overall Equipment Effectiveness (OEE). Meets today’s cyber security requirements. Opens-up use of AI.

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40G Ethernet MAC and PHY FPGA IP

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet is an industry standard and is compliant for media access control (MAC) and PHY (PCS+PMA) functions. It enables an FPGA to interface to another device over a copper or optical transceiver module.

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40G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency.

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