banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
Intellectual Property (IP) Digital Signal Processing / AI Artificial Intelligence Error Correction Filters /Transforms Floating Point Modulation Video and Image Processing Interfaces Audio / Video Communication Compute Express Link (CXL) Ethernet High Speed Networking / Security PCI Express (IP) Serial Memory Controllers DMA Flash SDRAM SRAM Soft Embedded Processors RISC V Transceivers & Basic Functions Clocks, PLLs and Resets Simulation, Debug and Verification Transceivers
By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

ATSC 8-VSB Modulator

The CMS0033 ATSC 8-VSB modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).

Aurora 64B/66B IP Core

The ALSE Aurora 64B/66B is a complete and fully compliant implementation of the published protocol. It allows to interconnect Altera FPGAs to Altera and other vendors FPGAs through High-Speed Serial links, from 1Gb/s to 800 Gb/s.

Aurora 8B/10B IP Core

The ALSE Aurora 8B/10B IP Core makes this open protocol available to all Altera FPGAs (that include transceivers).

AVB MILAN IP

Complete Certified MILAN IP in an SoC-FPGA.

Baseline JPEG Video Decoder IP Core

This compact, extremely efficient and low latency IP core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not require any processor nor any external memory.

Baseline JPEG Video Encoder IP Core

Very compact and very low latency JPEG/MPEG encoder ideal for video and still pictures. Output is fully standard and decoded by all viewers.

CAN-CTRL: CAN 2.0, CAN FD, & CAN XL Bus Controller Core

"The CAN-CTRL is a CAN bus controller compliant to Classical CAN, CAN FD, and CAN XL. The core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). Finally, the CAN-CTRL provides error analysis, diagnosis, maintenance, and optimization features. The CAN-CTRL is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready. "

CIC FPGA IP Core

The CIC FPGA IP core offers computationally efficient cores for extracting baseband signals.

Clock to PPS

Clock to Pulse Per Second Converter