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Adjustable Clock

Full standalone hardware only solution of an adjustable Counter Clock

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AES - Advanced Encryption Standard Engine

The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (CBC, CFB, CTR, ECB, LRW, and OFB). The core works with a pre-expanded key, or with optional key expansion logic. The AES core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs, with complete deliverables.

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AES-CCM: Authenticated Encrypt/Decrypt Engine

The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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AES-GCM: Authenticated Encrypt/Decrypt Engine

The AES-GCM IP core implements NIST Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). GCM is an authenticate-and-encrypt block cipher mode where a Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The core processes 128-bit blocks and is programmable for 128-, 192-, and 256-bit keys. Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S), more compact using a 32-bit datapath, requires 44/52/60 clocks for each data block (128/192/256-bit key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requires 11/13/15 clocks for each data block depending on key size. For high-throughput applications there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size.

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AES-P: Programmable Advanced Encryption Standard Engine

The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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AES-XTS: Storage Encrypt/Decrypt Engine

The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths. Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path. XTS (XEX-based Tweaked Codebook Mode with Ciphertext Stealing) is a mode of AES that has been specifically designed to encrypt fixed-size data where a possible threat has access to the stored data.

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ASCON-F: ASCON Authenticated Encryption & Hashing Engine

The ASCON-F IP is a compact, high-throughput HW core implementing the lightweight authenticated encryption with associated data (AEAD) & hashing algorithms of the Ascon v1.2 spec. A single instance supports encryption & decryption with Ascon-128 & Ascon-128a, as well as cryptographic hashing with Ascon-Hash & Ascon-Hasha. Operation mode, key, and nonce values are run-time programmable & can change per input block. The core provides simple I/O I/F, optionally bridged to AXI4-Stream or AXI4 Memory Mapped ports through CAST bridges. It synthesizes to ~11k gates & runs at over 2GHz in modern ASIC technologies. Excluding padding & initialization, throughput ranges from 5.3 to 16 bits/cycle, or 10.6 to 32Gbps at 2GHz, with higher throughput possible by instantiating multiple cores. Easy to use & integrate, following best coding & verification practices, has no multi-cycle or false paths, uses only rising-edge D flip-flops, no tri-states or SRAMs, and operates in a single clock/reset domain.

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ASRC: Audio Sample Rate Converter

The CAST ASRC (Audio Sample Rate Converter) is a compact, high-performance IP core that delivers precise digital audio conversion across a wide range of sample rates (8 kHz to 192kHz) while preserving signal integrity and minimizing distortion. Supporting both asynchronous and synchronous modes, it ensures seamless real-time streaming or high-speed batch processing for applications in professional audio, broadcast, telecommunications, automotive infotainment, gaming, and VR. The ASRC handles tens to hundreds of TDM channels, achieving ultra-low distortion with THD+N averaging -130 dB. With sub-100ms sync time and minimal latency, it provides transparent, studio-grade 24-bit audio conversion. Designed for easy integration into ASICs or FPGAs, it features AXI4-Stream for audio data, AXI-Lite/APB control interfaces, and optimized resource usage for cost-sensitive environments. Deliverables include Verilog RTL/netlist, testbenches, drivers, and documentation for rapid deployment

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CAN-CTRL: CAN 2.0, CAN FD, & CAN XL Bus Controller Core

"The CAN-CTRL is a CAN bus controller compliant to Classical CAN, CAN FD, and CAN XL. The core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). Finally, the CAN-CTRL provides error analysis, diagnosis, maintenance, and optimization features. The CAN-CTRL is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready. "

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