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ASRC: Audio Sample Rate Converter

The CAST ASRC (Audio Sample Rate Converter) is a compact, high-performance IP core that delivers precise digital audio conversion across a wide range of sample rates (8 kHz to 192kHz) while preserving signal integrity and minimizing distortion. Supporting both asynchronous and synchronous modes, it ensures seamless real-time streaming or high-speed batch processing for applications in professional audio, broadcast, telecommunications, automotive infotainment, gaming, and VR. The ASRC handles tens to hundreds of TDM channels, achieving ultra-low distortion with THD+N averaging -130 dB. With sub-100ms sync time and minimal latency, it provides transparent, studio-grade 24-bit audio conversion. Designed for easy integration into ASICs or FPGAs, it features AXI4-Stream for audio data, AXI-Lite/APB control interfaces, and optimized resource usage for cost-sensitive environments. Deliverables include Verilog RTL/netlist, testbenches, drivers, and documentation for rapid deployment

Baseline JPEG Video Decoder IP Core

This compact, extremely efficient and low latency IP core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not require any processor nor any external memory.

Baseline JPEG Video Encoder IP Core

Very compact and very low latency JPEG/MPEG encoder ideal for video and still pictures. Output is fully standard and decoded by all viewers.

CAN-CTRL: CAN 2.0, CAN FD, & CAN XL Bus Controller Core

"The CAN-CTRL is a CAN bus controller compliant to Classical CAN, CAN FD, and CAN XL. The core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). Finally, the CAN-CTRL provides error analysis, diagnosis, maintenance, and optimization features. The CAN-CTRL is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready. "

CCSDS 231.0 LDPC Encoder and Decoder

The CCSDS 231.0 LDPC IP core supports the LDPC coding schemes and is an ideal fit for further applications with highest demands on forward error correction.

CCSDS LDPC Encoder and Decoder

The Creonic CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard.

CCSDS SCCC Turbo Encoder and Decoder

The Creonic CCSDS SCCC Turbo IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.

CIC FPGA IP Core

The CIC FPGA IP core offers computationally efficient cores for extracting baseband signals.

Clock to PPS

Clock to Pulse Per Second Converter