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100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

MLE 100G TCP/IP is a stand-alone TCP/IP Stack Full Accelerator Subsystem allowing 100Gbps communication at full line rate and low latency. It includes TCP, IP, MAC Layer, supports 128-bit wide full duplex data width, and pipelines all-RTL implementation for high throughput and ultra low Latency.

100G UDP IP Core

iWave’s UDP/IP Core is a high-performance IP solution that enables hardware-accelerated UDP communication over Ethernet, achieving data rates up to 40Gbps. Designed for FPGA-based applications, it ensures low-latency, processor-independent data streaming and network communication. This makes it ideal for real-time media, sensor, and industrial networking use cases.

100G UDP IP Stack

Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs

100G UDP Offloading Engine (UDP100G-IP)

UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP100G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

100GbE TCP Offloading Engine IP core (TOE100G-IP)

100GbE TCP Offloading Engine (TOE100G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management.

10G UDP Offloading Engine (UDP10G-IP)

UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP10G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

10GBASE-R PHY FPGA IP

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

10GBASE-R PHY FPGA IP

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

10GbE TCP Offloading Engine IP core (TOE10G-IP)

10GbE TCP Offloading Engine (TOE10G) IP core is the epochal solution implemented without CPU. Typically, TCP/IP stack consumes high valuable resource of CPU workloads. With its pure hardware logic, TOE10G IP can entirely take over the TCP/IP stack operation with high proven throughput for 10GbE communication.