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Digital Signal Processing / AI Artificial Intelligence Error Correction Filters /Transforms Floating Point Modulation Video and Image Processing
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100 Gbit/s IEEE 802.3bj RS Encoder/ Decoder

The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.

100G UDP IP Stack

Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs

10GbE TCP Offloading Engine IP core (TOE10G-IP)

10GbE TCP Offloading Engine (TOE10G) IP core is the epochal solution implemented without CPU. Typically, TCP/IP stack consumes high valuable resource of CPU workloads. With its pure hardware logic, TOE10G IP can entirely take over the TCP/IP stack operation with high proven throughput for 10GbE communication.

1G-100G Robo/TSN Industrial Network Virtualization and Acceleration for Converged OT/IT - MLE FPGA Design Services

Openness has greatly benefited other industries like automotive, aerospace, banking, datacenters, and finally OT: No vendor lock-in, higher flexibility and better long-term-availability. Cost reduction for Overall Equipment Effectiveness (OEE). Meets today’s cyber security requirements. Opens-up use of AI.

3D LUT Altera® FPGA IP

The 3D Look-Up Table (LUT) Altera® FPGA IP, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance, resource-efficient solution for video color space conversion, dynamic range adjustment, chroma keying, and artistic effect generation, enabling superior image quality in broadcast and professional video applications.

4G LTE/LTE-A CTC

Creonic’s LTE/LTE-A IP core is an advanced, customer proven implementation of the standardized 3GPP turbo code.

5G LDCPC-V FPGA IP

Low-density parity-check (LDPC) IP helps transmit and receive messages over noisy channels. This IP implements LDPC codes compliant with the 3rd generation partnership project 5G specification.

800G Ethernet IP core

800G IP core for Agilex™ 7 I/M series FPGAs with 112Gbps transceivers. ETC-compliant 800Gbps Ethernet for networks, switches, and NICs using eight 112Gbps lanes and a single 800G MAC.

Adjustable Clock

Full standalone hardware only solution of an adjustable Counter Clock