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Aurora 8B/10B IP Core

The ALSE Aurora 8B/10B IP Core makes this open protocol available to all Altera FPGAs (that include transceivers).

CDC - Customizable Display Controller IP Core Family

Highly customizable MIPI-DPI compliant display controller supporting on-the-fly image composition from several input sources (images in memory or AXI4 Stream) with a powerful set of image processing features.

CoaXPress Device IP Core

IP Core for CoaXPress camera applications with speed support from 1 Gbps up to 100 Gbps.

CoaXPress Host IP Core

IP Core for CoaXPress host/receiver applications with speed support from 1 Gbps up to 100 Gbps.

CoaXPress-over-Fiber Bridge Device IP core

Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer.

CoaXPress-over-Fiber Bridge Host IP core

Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer.

CVI - Customizable Video Input Controller IP Core Family

Video input controller capturing an RGB or ITU-R BT.656/BT.601 video input stream to memory with configurable functions, e.g., scaling, color format conversion, clipping, dithering.

DISPLAY PORT IPs

Logic Fruit's Display Port Transmitter & Receiver IP Cores support multiple line rates up to 8.1 Gbps. The IP cores have been developed as per Display Port specifications DP2.0/eDP1.5.

DVB-S2 IP

The DVB-S2 (Digital Video Broadcasting - Satellite - Second Generation) IP Core offers a high-performance, fully compliant, and cost-efficient solution for satellite-based communication systems. Designed to implement the ETSI EN 302 307 standard, our DVB-S2 IP Core supports all key features of the specification, including powerful LDPC/BCH Forward Error Correction, adaptive coding and modulation (ACM), and multi-stream transmission—enabling robust and bandwidth-efficient data transmission over satellite links.