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GEDEK (Ethernet Data Exchange Kit) IP Core

Connect your FPGA to Ethernet without any processor and 100% efficiency !

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GigE Vision 2.x Device IP Core

IP Core for GigE Vision 2.x compliant camera applications.

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GigE Vision 2.x Host IP Core

IP Core for GigE Vision 2.x compliant host/receiver applications.

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GigE Vision 3.0 Device IP with RoCEv2 Streaming

IP Core for GigE Vision 3.0 camera applications with support of remote DMA streaming using RoCEv2 protocol up to 25Gbps network speed.

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H.264 Baseline, Main and High Profiles Single- and Multi-channel Encoder IP Core

The H264-HP-E core from Alma Technologies is an advanced and self-contained ITU-T H.264 High profiles hardware encoder.

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HDMI IP Core

The HDMI Altera® FPGA IP core delivers high-performance, standards-compliant support for the latest HDMI specifications, enabling seamless transmission of high-definition audio and video over a single interface. It provides a robust and flexible solution for integrating next-generation video display connectivity into Altera FPGA designs.

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HDMI Reciver Transmitter Cores

The HDMI Transmitter core is has a very low footprint and works at various speed depending on application being used.

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I3C-SC: MIPI I3C Basic Secondary Controller

The I3C-SC core is a versatile MIPI® I3C Secondary Controller compliant with the latest I3C BasicSM specification. It can operate as a bus controller or target, supporting SDR communication while tolerating HDR traffic, and coexisting with legacy I2C devices. As a target, it autonomously handles Common Command Codes (CCCs), supports dynamic or static addressing, Hot-Join, and In-Band Interrupts. The core offers two operating modes: normal mode, where data is exchanged via an APB subordinate interface, and I3C-to-AHB bridging mode, where private I3C/I2C transfers are converted into AHB transactions for remote monitoring, configuration, or data exchange without software intervention. Flexible synthesis-time and run-time options allow customization of features, size, and behavior. With industry-best design practices, clean clock domain crossings, and FPGA validation, the I3C-SC ensures reliable, low-risk integration into ASIC or FPGA designs.

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I3C-T: MIPI I3C Basic Target

The I3C-T core is a flexible, target-only MIPI® I3C controller compliant with the latest I3C-BasicSM specification. Supporting SDR communication while tolerating HDR traffic, it interoperates with legacy I2C devices and can optionally function as an I2C target. The core autonomously handles relevant Common Command Codes (CCCs), supports dynamic or static addressing, Hot-Join, and In-Band Interrupts. It offers two operating modes: normal mode, where data transfers use an APB subordinate interface, and I3C-to-AHB bridging mode, where private I3C/I2C transactions are automatically converted into AHB accesses for remote monitoring, configuration, debug, or data exchange without software intervention. With both synthesis-time and run-time configurability, the I3C-T adapts to application needs while minimizing footprint. Designed with best coding practices, clean clock domain crossings, and FPGA validation, it ensures reliable, low-risk integration.

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Showing 19-27 of 68 Offerings