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IPMX Core

Nextera-Adeas' industry-leading IPMX FPGA IP cores contain everything needed to IPMX-Enable your new or existing products quickly and easily. A full IPMX Certified reference/demo design project is provided along with all of the drivers, daemons, system control software, and a Web GUI so customers can start with a working system and customize to their needs. Design services are also available to help accelerate time to market.

IPP-SS115A-BR – SAS 1-to-1 Speed Bridge with Sandbox IP

A high-performance SAS 1-to-1 Speed Bridge (up to 12G) featuring a unique "Sandbox" area for custom user logic, enabling real-time data manipulation, filtering, and protocol translation between SAS/SATA hosts and targets.

JPEG-DX-F: Ultra-Fast Baseline and Extended JPEG Decoder

This JPEG decompression IP core supports the Baseline & Extended Sequential DCT modes of the ISO/IEC 10918-1. It is scalable and ultra-high-performance, while handles extremely high pixel rates of JPEG images and video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. It can process from 2 to 32 color samples per clock cycle. Paired with the JPEG-EX-F Encoder Core provide an extremely cost-effective solution. Standalone operation, once programmed, parsing marker segments, decompressing coded data and reporting back the image format. SoC integration is straightforward (standard AMBA I/F - AXI Streaming & APB Slave). CAST’s IP Integration Services are also available for JPEG subsystems (the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST).

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KJN-XL1_ENC(JPEG)

Our "KJN-XL1_ENC" is a latest JPEG standard, offering a JPEG IP core that achieves both high compression and high image quality.

MEV RSU

PCIe Remote System Update

MIPI CSI-2

Qbit Labs’ MIPI CSI-2 IP Core and Controller provides high-speed, low-power camera connectivity for advanced imaging applications. Fully compliant with the MIPI CSI-2 standard, it enables scalable, reliable data transfer from image sensors with a flexible and integration-ready architecture. Ideal for AI/ML vision systems, embedded platforms, automotive imaging, and industrial camera solutions.

MIPI CSI-2 Receive Core

Proven MIPI-CS2 Receive Core

MIPI CSI-2 Transmit Core

Proven MIPI CSI2-TX IP Core for Altera devices

MIPI D-PHY IP

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.