SHA-3: Secure Hash Crypto Engine
The SHA-3 IP core is a high-throughput, area-efficient hardware accelerator for SHA-3 cryptographic hashing, compliant with NIST FIPS 180-4 and FIPS 202. It operates independently of a host processor, using AMBA® AXI4-Stream interfaces for input and output. An optional AXI4-Stream to AXI4 Memory Mapped bridge, with or without DMA, can be used. A single core instance implements all fixed-length and extendable-output hash functions, with function and output length (up to 2 GB) selectable at runtime per input message. The core is highly configurable at synthesis, including bus width and SHA-3 permutation rounds per cycle, enabling throughput–area trade-offs. One permutation per cycle processes 50 bits per cycle, scaling to over 100 Gbps with multiple permutations in modern ASICs. Fully synchronous, single-clock, scan-ready, LINT-clean, it uses only rising-edge flip-flops, with no false or multi-cycle paths, simplifying integration and verification.