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FIR II FPGA IP Core

The FIR II IP cores provide a fully-integrated finite impulse response (FIR) filter function optimized for use with Altera FPGA devices.

Interlaken IP

Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.

Low Latency Ethernet 100G MAC and PHY FPGA IP

Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.

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Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

Multi-Rate Ethernet PHY FPGA IP

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.

NCO FPGA IP Core

Numerically Controlled Oscillator IP for discrete-time, discrete-valued representation of a sinusoidal waveform.

Nios V Processors

Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source RISC-V Architecture to FPGA environments. By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.

Reed Solomon II FPGA IP Core

The Reed Solomon II IP offers a fully parameterizable Reed Solomon encoder and decoder.

SDI II FPGA IP

The Altera SDI II FPGA IP core enables high-performance serial digital interface (SDI) transmission and reception across SD, HD, and 3G to 12G video rates.