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FFT FPGA IP Cores

The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.

GTS Ethernet Hard IP

The GTS Ethernet Hard IP (EHIP) allows fast, flexible, and high-performance Ethernet implementation with minimal FPGA resource utilization. The EHIP includes a configurable, hardened protocol stack for Ethernet compatible with the IEEE 802.3-2018 Standard and the 25G/50G Ethernet Specification from the 25 Gigabit Ethernet Consortium.

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Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

Multi-Rate Ethernet PHY FPGA IP

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.

Triple-Speed Ethernet FPGA IP

A complete 10/100/1000 Mbps Ethernet IP with flexible IP options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA.