IP Core Support
Quartus II Software Arria 10 Edition v14.0 provides a full complement of 20 nm-optimized intellectual property (IP) cores to speed up your design cycle times. Altera’s best-in-class IP cores optimized for Arria 10 FPGAs and SoCs include 100G Ethernet, 300G Interlaken / Interlaken Look-Aside, and PCI Express® Gen3 IP cores. When implemented in Altera's Arria 10 FPGAs and SoCs, these best-in-class IP cores deliver the highest performance in the FPGA industry. For more information, visit the What’s New for IP in Quartus II Software Arria 10 Edition v14.0 web page.
Quartus II Software Arria 10 Edition v14.0 features an all new hard processor system (HPS) Qsys MegaWizard that allows designers to configure the processor and peripherals in the Arria 10 SoC HPS. Board designers can begin prototyping PCB designs for Arria 10 SoCs with final pin tables and leverage the full pin compatibility between Arria 10 FPGA and SoC devices. Software applications developers can take advantage of the code compatibility between 28 nm Cyclone V and Arria V SoCs and 20 nm Arria 10 SoCs. They can reuse the extensive application code, tools, operating system support, and development kits available for 28 nm SoCs for rapid software development and prototyping.
About Arria 10 FPGAs and SoCs
Altera’s Arria 10 FPGAs and SoCs deliver the highest performance at 20 nm, offering a one speed grade performance advantage over competing devices. Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous-generation FPGAs and SoCs, and offer the industry’s only hardened floating-point digital signal processing (DSP) blocks. To learn more, visit the Arria 10 FPGAs and SoCs web page.