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Result 1-10 of 8904 results in Knowledge Base.
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<12345>

Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 Devices

Intel FPGA and SoC > Support > Support Resources >... > Solutions
>Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 Devices. ...

https://www.altera.com/support/support-resources/knowledge-base/solutions/fb367319.html2017-10-13

What assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Arria 10 ES2, ES3 or production device?

Intel FPGA and SoC > Support > Support Resources >... > 2017
>What assignments do I need for a PCIe Gen1, Gen2 ...

https://www.altera.com/support/support-resources/knowledge-base/ip/2017/what-assignments-do-i-need-for-a-pcie-gen1--gen2-or-gen3-design-.html

Why does my Arria 10 PCIe Hard IP link width downtrain?

Intel FPGA and SoC > Support > Support Resources >... > 2017 >Why
does my Arria 10 PCIe Hard IP link width downtrain? ...

https://www.altera.com/support/support-resources/knowledge-base/ip/2017/why-does-my-arria-10-pcie-hard-ip-link-width-downtrain-.html?cq_ck=1501066300630

What assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Arria 10 ES2, ES3 or production device?

Intel FPGA and SoC > Support > Support Resources >... > 2017
>What assignments do I need for a PCIe Gen1, Gen2 ...

https://www.altera.com/support/support-resources/knowledge-base/ip/2017/what-assignments-do-i-need-for-a-pcie-gen1--gen2-or-gen3-design-.html?utm_source=Altera&utm_medium=newsletter&utm_campaign=FACTS&utm_content=NA_what_assignments_do_i_need_pcie_KI_11_07_2017

why does my design hit into data corruption failure on Double Data rate Input path when there are no timing violation reported in timing report?

Intel FPGA and SoC > Support > Support Resources >... > 2017
>why does my design hit into data corruption failure ...

https://www.altera.com/support/support-resources/knowledge-base/tools/2017/arria-10-io_48-and-ioaux-timing-miscorrelation0.html

Why does my Arria 10 SoC design hang in bootloader or when accessing FPGA-to-SDRAM bridge?

Intel FPGA and SoC > Support > Support Resources >... > 2017 >Why
does my Arria 10 SoC design hang in bootloader ...

https://www.altera.com/support/support-resources/knowledge-base/embedded/2017/why-does-my-arria-10-soc-design-hang-in-bootloader-or-when-acces.html

Have the Arria 10 device timing models for input paths with calibrated I/O standards been changed since the release of Quartus Prime software version 16.1 Update 1?

Intel FPGA and SoC > Support > Support Resources >... > 2017 >Have
the Arria 10 device timing models for input paths ...

https://www.altera.com/support/support-resources/knowledge-base/tools/2017/have-the-arria-10-device-timing-models-for-input-paths-with-cali.html

How and when can I enable the FPGA2SDRAM bridge on Cyclone V SOC and Arria V SOC devices?

Intel FPGA and SoC > Support > Support Resources >... > 2016 >How
and when can I enable the FPGA2SDRAM bridge ...

https://www.altera.com/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html?utm_source=Altera&utm_medium=newsletter&utm_campaign=FACTS&utm_content=NA_how_can_i_enable_KI_15_08_2016

How to compensate the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?

Intel FPGA and SoC > Support > Support Resources >... > 2017
>How to compensate the jitter of PLL cascading or ...

https://www.altera.com/support/support-resources/knowledge-base/tools/2017/fb470823.html

Why does my Arria 10 SoC industrial grade device fail to boot at low temperature?

Intel FPGA and SoC > Support > Support Resources >... > 2016
>Why does my Arria 10 SoC industrial grade device ...

https://www.altera.com/support/support-resources/knowledge-base/embedded/2016/why-does-my-arria-10-soc-industrial-grade-device-fail-to-boot-at.html

<12345>

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