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1
Why do I see hold time violations when using the 10GBASE ...

Intel FPGA and SoC > Support > Support Resources >... > 2018 >Why
do I see hold time violations when using the 10GBASE ...
www.altera.com/support/support-resources/knowledge-base/ip/2018/why-do-i-see-hold-time-violations-when-using-the-10gbase-kr-phy-.html - 73k - 2018-05-10 -

Source: Altera

2
Can I use a 161 MHz clock for the Avalon-M clock of the Stratix ...

Intel FPGA and SoC > Support > Support Resources >... > 2017
>Can I use a 161 MHz clock for the Avalon-M clock ...
www.altera.com/support/support-resources/knowledge-base/ip/2017/can-i-use-a-161-mhz-clock-for-the-avalon-m-clock-of-the-stratix-.html - 73k - 2017-06-15 -

Source: Altera

3
Why do I see the following message when attempting to start ...

Intel FPGA and SoC > Support > Support Resources >... > solutions
>Why do I see the following message when attempting ...
www.altera.com/support/support-resources/knowledge-base/solutions/rd09132016_439.html - 77k - 2016-10-10 -

Source: Altera

4
Why does the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP ...

Intel FPGA and SoC > Support > Support Resources >... > solutions
>Why does the 1G/2.5G/5G/10G Multi-rate Ethernet ...
www.altera.com/support/support-resources/knowledge-base/solutions/rd07062016_250.html - 74k - 2016-08-19 -

Source: Altera

5
Incorrect Product ID for 10GBASE-KR PHY MegaCore ...

Intel FPGA and SoC > Support > Support Resources >... > solutions >Incorrect
Product ID for 10GBASE-KR PHY MegaCore Function. ...
www.altera.com/support/support-resources/knowledge-base/solutions/fb128353.html - 73k - 2013-07-02 -

Source: Altera

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