- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... Due to a problem with the Intel® Serial Digital Interface (SDI) II IP core TX,
sync bits are not correctly inserted into the ADF words when operating in ...
... Quartus Prime Pro Edition Version 16.1 does not support DisplayPort
IP core, HDMI IP core, or SDI II IP core. Description. ...
... This issue is fixed in version 16.0 Update 2 of of the SDI II IP core and in
the design example\'s reconfiguration management files.
... Will the SDI MegaCore compile successfully if either the project directory or
Quartus II software installation directory contains spaces? Description. ...
... For details on how to run the SDI demonstration design you should refer to
AN: 339 Serial Digital Interface Demonstration for Stratix II GX Devices ...
... incorrectly when receiving SD-SDI with a high jitter source. Both SDI®
and SDI II IP Cores are affected. Workaround/Fix. ...
... Workaround/Fix. To work around this issue, use the generated
sdi_ii_ed_reconfig_a10 file from version 15.1 Update 2 of the SDI II IP core. ...
... SDI with Enabled Transmitter Clock Multiplexer will Fail Compilation in the
Quartus II Software due to Missing Constraint Parameters. Description. ...
... The Quartus II software SDI MegaWizard Plug-In Manager does not display
a vertical scroll bar when resized with a screen resolution of 1024x768. ...
... How do I connect the detected_rate and detected_rate_in signals from
the Serial Digital Interface (SDI) MegaCore? Description. ...