- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... Which mode should I select for Sync signals with SDI input in CVI II IP?
Description. ... The preset settings for SDI will be corrected in a future release.
... Why is the dummy RX PHY required for reconfiguration missing from the Intel®
FPGA SDI II IP generated Multi Rate Bidirectional mode design ...
... How do I connect the detected_rate and detected_rate_in signals from
the Serial Digital Interface (SDI) MegaCore? Description. ...
... What is the reset sequence of the SDI RX instance in the SDI MegaCore
function? Description. The reset sequence of the ...
... When using the SDI RX and TX MegaCore function (independent RX & TX
instances packed into the same channel), can I reset only the RX ...
... Description. The aud_z signal from the Altera® Serial Digital Interface (SDI)
Audio Extract MegaCore® is not required. You can ignore this signal. ...
... Can I use rx_clk output from RX SDI MegaCore as input to tx_serial_refclk
of TX SDI MegaCore during parallel video signal loopback? Description. ...
... How is the FIFO being used during the transfer of rx_data from the RX SDI
MegaCore to tx_data of the TX SDI MegaCore? Description. ... Figure 1. SDI. ...
... What is the behavior of the frame_locked output signal for the Serial
Digital Interface (SDI) MegaCore? Description. The ...
... Will the SDI MegaCore compile successfully if either the project directory or
Quartus II software installation directory contains spaces? Description. ...