- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... Why does the HDMI* Intel® TX IP core send incorrect AVI, VSI or AI information
from sidebands when the checksum is 0? Description. ...
... Why do I see timing violations in the Intel® Arria® 10 and Intel® Cyclone®
10 HDMI design example? Description. When ...
... Why Does HDMI RX Fail to Lock to Progressive Video With Unaligned
Vsync And Hsync? Description. If the HDMI RX IP ...
... Why is the Intel® HDMI* IP RX vid_lock signal deasserted when the
video timing geometry is inconsistent? Description. ...
... Why are the Intel® FPGA HDMI IP Core Trailing Scrambled Data Island
Guardbands For Channel 1 & 2 Not Encoded Correctly? Description. ...
... Can I use a transceiver RX Pin as a CDR REFCLK for the HDMI Design
Example Receiver Interface (Sink) on Arria 10 and Cyclone 10 devices? ...
... Can I use a transceiver RX Pin as a Tx PLL REFCLK for the HDMI Design
Example transmitter interface (Source) on Arria 10 and Cyclone 10 ...
... Why do I see an error when running the Design Assistant on the HDMI design
in Intel® Quartus® Prime standard software? Description. ...
... Why does the Arria 10 HDMI Example Design intermittently fail read transfers
after data rate switching above 5Gbps? Description. ...
... 2017 >Timing violation in ls_clk clock domain of HDMI RX core IP. ... Timing
violation in ls_clk clock domain of HDMI RX core IP. Description. ...