- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
Intel FPGA and SoC > Support > Support Resources >... > solutions >Design
Space Explorer II compilation errors: "[Errno 99] Cannot assign ...
Intel FPGA and SoC > Support > Support Resources >... > solutions
>Compilation of a Design with BluePrint Platform Designer-Generated QSF ...
... If you are using a 3rd party programmer tool or your own solution, you must
set the non-volatile configuration registers accordingly. ...
... calculate decoupling for currents less than 0.001mA. Entering 0.001mA
will not significantly burden your decoupling solution.
... solutions >Using BluePrint's Autoplace All feature to place the periphery
generates assignments that might cause an internal error in quartus_syn. ...
... in a future version of the Intel® Stratix® 10 Avalon®-ST and Single Root I/O
Virtualization (SRIOV) Interface for PCIe* Solutions User Guide.
Intel FPGA and SoC > Support > Support Resources >... > solutions >SEVERE:
No file/ip_name.spd. Type: Answers, Errata Area: Tools. ...
... solutions >What soldering profile does Altera recommend for surface mount
devices (SMDs)? Type: Answers Area: Component. ...
... solutions >Why is Altera® USB Blaster not detected by Quartus® Programmer
when it is recognized correctly in Device Manager? ...
... solutions >Some Designs with User Partitions and State Machines Might
Encounter Fatal Errors during Analysis and Synthesis. ...