- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
- v15.1 Update 2
Intel FPGA and SoC > Support > Support Resources >... > Solutions >Can
mechanical samples be used for anything other than practicing reflow? ...
... Solutions >Performance Risk ... The following patch provides a solution to the
Triple Speed Ethernet IP variant with LVDS I/O for PMA implementation ...
... Solutions >What is the maximum downward pressure that can be applied to
the top of Altera BGA packages? Type: Answers Area: Component. ...
... Controller IP with the Enhanced compression option. Workaround/Fix. To
solve this problem, use one of the following solutions: ...
... Due to a mistake in the 2017.05.08 revision of the Intel® Stratix® 10
Avalon®-MM Interface for PCIe® Solutions User Guide, the rxm_irq port ...
... simulation. For modes up to Gen3x8, follow the instructions in the Stratix
10 Avalon-ST Interface for PCIe Solutions User Guide. ...
... To be able to use Pre-emption feature, Vectored Interrupt Controller would
be the only solution to do so, since IIC does not support pre-emption ...
... Resources >... > Solutions >Why does my Cyclone III FPGA fail to access
the EPCS device using the EPCS Controller module? ...
... Resources >... > Solutions >RapidIO MegaCore Function User
GuideTestbench Instructions for ModelSim Require Modification. ...
... Solutions >RapidIO MegaCore Function User Guide Has Incorrect
Information About the Port 0 Error and Status CSR. ...