- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
- v15.1 Update 2
- v15.1 Update 1
... SoC Embedded Software; Nios Embedded Software. All Products.
Industry Solutions: Automotive; Broadcast; Computer & ...
Intel FPGA and SoC > Support > Support Resources >... > solutions >When
writing the fabric configuration data (.pof) to the Configuration via ...
... Resources >... > solutions >Does Altera provide support for Multi-port
Front End IP implemented in the core FPGA fabric? ...
... solutions >What is the maximum downward pressure that can be applied to
the top of Altera BGA packages? Type: Answers Area: Component. ...
... Resources >... > solutions >Why is my Arria 10 10AX115 production
device IDCODE detected as 0x02E060DD? Device ...
... reset controller, please refer to the related solution below: This issue is fixed
in v13.1.2 and later of the the Quartus® II software. Related Solutions. ...
... around this problem in the Quartus II software version 13.0, download and
install patch 0.dp2 from the related solution below. ... Related Solutions. ...
... solutions >Warning message: "Can't pack non-peripheral register
<name> to I/O pin <name> — too few peripheral buses.". ...
... solutions >Does Altera combine and ship devices with different date codes
in one unit box? Type: Answers Area: Component. ...
... Resources >... > solutions >Internal Error: Sub-system: EDA, File:
wsc_hierarchy_builder.cpp, Line: 1928 Can not find hierarchy info. ...