- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
- v15.1 Update 2
... Resources >... > Solutions >How can I obtain a Material Declaration for Altera®
devices? Device ... Declaration page. Related Solutions. ...
... Resources >... > Solutions >Why is my Cyclone V or Stratix V Altera_PLL
reset port is inverted in simulation? ... vo>. Related Solutions. ...
... Solutions >Does Altera combine and ship devices with different date codes
in one unit box? Type: Answers Area: Component. ...
... warning icon next to it. Workaround/Fix. See the related solution for the
workaround. Related Solutions. Why do MSI's not work ...
... Resources >... > Solutions >Error (175001): Could not place 1 IOPLL,
which is within Altera IOPLL <instance name> ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >Why
does the Quartus II fitter report display "unused" in the Termination ...
... This problem does not affect earlier versions of the Quartus II software, but
see the related solution below for a similar problem ... Related Solutions. ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >Error
reported by S-function <function> in <user module>: No descriptive text ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >What
are the required MSEL pin settings on my FPGA device when ...
... Solutions >Why do memory reads and writes fail to my PCI Express
Endpoint enabled BAR locations? ... Related Solutions. ...