- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... solutions >Does the stand ... For more information refer to AN 425: Using the
Command-Line Jam STAPL Solution for Device Programming (PDF).
... solutions >How can I create a Raw Programming Data file for remote
update of a specific CFM location in MAX 10 devices? ...
... solutions >What are the voltage requirements for the voltage sensor pins VSIGP
and VSIGN, when used in unipolar input mode in Arria 10 devices? ...
... Resources >... > solutions >Is there a known problem with Arria 10 fPLL
simulation when the clock switchover feature is enabled? ...
Intel FPGA and SoC > Support > Support Resources >... > solutions >Internal
Error: Sub-system: ASMCC, File: /quartus/comp/asmcc/asmcc_bitfield ...
... Resources >... > solutions >Why does the EMIF toolkit fail to recognize
the memory interface when it is generated in Qsys? ...
... solutions >Error: (vsim-3058) The width (<verilog width>) of Verilog port
'scaninb' does not match the array length (31) of its VHDL connection. ...
... Resources >... > solutions >Why can't I simulate the Arria II IP Compiler for
PCI Express in Quartus 13.1? ... software. Related Solutions. ...
... reconfiguration for Stratix V, Arria V and Cyclone V devices. This issue is fixed
in Quartus® II software version 13.1. Related Solutions. ...
Intel FPGA and SoC > Support > Support Resources >... > solutions >Why
does transceiver reconfiguration fail for Arria V, Cyclone V, and Stratix V ...