- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... Resources >... > Solutions >How can I obtain a Material Declaration for Altera®
devices? Device ... Declaration page. Related Solutions. ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >Why
is the UniPHY based memory controller design not meeting timing? ...
... Solutions >Warning message: "Can't pack non-peripheral register
<name> to I/O pin <name> — too few peripheral buses.". ...
... Solutions >Is there an issue with the output clock frequency if you set the duty
cycle values other than 50% in the Altera PLL megafunction? ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >Error
reported by S-function <function> in <user module>: No descriptive text ...
... Solutions >Error: pcie_hard_ip_0_pcie_bfm_0: altera_pcie_bfm_qsys
does not support generation for VHDL Simulation. ...
... Description. No, each fPLL can only drive a single refclk input on the cascade
clock network of Cyclone® V GX devices. Related Solutions. ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >What
are the required MSEL pin settings on my FPGA device when ...
... Support Resources >... > Solutions >How to manually instantiate the hard
input FIFO from ALTDQ_DQS2 in Stratix V? Device ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >Error:
Can't recognize silicon ID for device 1. ... Related Solutions. ...