- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... Solutions >When in the configuration process will the CRC_ERROR pin be
driven low if enabled? Type: Answers Area: Component. ...
... Solutions >Can the dual-purpose configuration data pins be used as
user I/O if Partial Reconfiguration mode is enabled? ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >ALOG:
Error: VCP2964: Parameter initializer must be a constant ...
... Solutions >Where can I find the coplanarity specification (flatness from edge
to edge) for Altera devices? Type: Answers Area: Component. ...
... Resources >... > Solutions >Why do I see setup time violation on my
I/O paths in the Quartus II software version 13.0 SP1? ...
... Resources >... > Solutions >Is 8b10b encoding supported in the Arria
V, Cyclone V or Stratix V transceiver toolkit? Device ...
... Support Resources >... > Solutions >Why are some pins of adjacent banks
placed on different edges of the package? Device ...
Intel FPGA and SoC > Support > Support Resources >... > Solutions >Where
can I get Quartus II software version 14.0 32-bit installer? ...
... Resources >... > Solutions >Is there a known problem with Arria 10 fPLL
simulation when the clock switchover feature is enabled? ...
... Solutions >What are the connection guidelines for the REFCLK pin
(GXBR4F) in the Arria 10 10AX115NF40 package? ...