- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... Resources >... > solutions >Error in 'mdm/HDLImport' while executing
C MEX S-function 'sGeneric', (mdlStart), at time 0.0. ...
... Resources >... > solutions >Why does my 1G/10G or 10GBASE-KR PHY
design fail Link Training in Verilog HDL simulation? ...
Intel FPGA and SoC > Support > Support Resources >... > solutions >Why
do I observe read errors with my UniPHY based memory controller IP ...
Intel FPGA and SoC > Support > Support Resources >... > solutions >How
can I use the LLM feature on Enpirion Power SoC devices? ...
... correctly connected. Workaround/Fix. Make sure the MPFE clock and
reset ports are properly connected. Related Solutions. ...
... Resources >... > solutions >What are the recommended rise and fall time
specifications for Altera® devices? ... dependent. Related Solutions. ...
Intel FPGA and SoC > Support > Support Resources >... > solutions
>What is the UL rating of Enpirion Power SoC devices? ...
... solutions >Why does my third-party PCI Express Bus Functional Model (BFM)
flag invalid symbol after End of Data Stream (EDS) token? ...
... solutions >msvcrt.lib(chkstk.obj) : fatal error LNK1112: module machine
type 'X86' conflicts with target machine type 'x64'. ...
... solutions >AN661: Implementing Fractional PLL Reconfiguration with
ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions: Known Issues. ...