- Stratix 10
- Stratix V E
- Stratix V GT
- Stratix V GS
- Stratix V GX
- Arria 10 SX
- Arria 10 GT
- Arria 10 GX
- Arria V ST SoC
- Arria V SX SoC
- Arria V GT
- Arria V GX
- Arria V GZ
- Cyclone 10 GX
- Cyclone V SE SoC
- Cyclone V ST SoC
- Cyclone V SX SoC
- Cyclone V E
- Cyclone V GT
- Cyclone V GX
- MAX 10
- MAX V
Quartus Prime Software Versions
Issues marked as Active in chosen release will be shown (found in earlier and not fixed, or found in)
- v16.0 Update 2
- v16.0 Update 1
... Why does my Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL
simulation hang in the reset state? Description. Your ...
... What transceiver PMA blocks are used in the Intel® Arria® 10 device
internal serial loopback path? Description. The Intel ...
... Last Modified: May 24, 2018. How to add the per-pin assignment to
preserve unused transceiver channels? Description. ...
... 2017 >Which IBIS_AMI model should I use to simulate the transceiver
links for Arria 10 SoC based devices? Device ...
... there any problems when selecting the routing overlay option in the Quartus
Prime Chip Planner for Arria 10 device ATX and FPLL HSSI elements? ...
... Why does the Stratix 10 H-tile Transceiver Native PHY IP show incorrect
magnitude range of VOD ? Description. Due to ...
... Can I use a transceiver RX Pin as a CDR REFCLK for the HDMI Design
Example Receiver Interface (Sink) on Arria 10 and Cyclone 10 devices? ...
... How do I add Intel® Stratix® 10 L-Tile and H-Tile device transceiver
PMA assignments to my QSF file? Description. You ...
... Can I use a transceiver RX Pin as a Tx PLL REFCLK for the HDMI Design
Example transmitter interface (Source) on Arria 10 and Cyclone 10 ...
... What is the minimum transceiver reference clock frequency for an Arria
10 device fPLL? Description. The minimum refclk ...