Multichannel Farrow Filter v9.1 README File This readme file contains the following sections: o Package Contents o Tool Requirements o General Description o Simulation in Simulink o Release History o Design Examples Disclaimer o Contacting Altera Package Contents ================ Altera Multichannel Farrow Filter v9.1 Design Example Files in this zip download include: o farrowm.mdl - DSP Builder Advanced Blockset design file for multiple channel farrow sample rate change filter o setup_farrowm.m - MATLAB script to configure initialization and parameters of farrow.mdl o stop_farrowm.m - MATLAB script to plot Farrow resampling filter output and compare it with input waveform Tool Requirements ================= This design example requires the following software package: o Quartus II 9.1 o DSP Builder Advanced Blockset v9.1 o MATLAB/Simulink version R2009a (Design verified in R2009a; DSP Builder Advanced Blockset requires 2007a or later) Please contact your local sales representative if you do not have one of these software tools. General Description ============================= The multichannel Farrow filter design example demonstrates how to use Altera DSP Builder Advanced Blockset (DSPB-AB) to implement a multichannel sample rate conversion filter based on Farrow structure. Sample rate conversion has a wide range of applications such as wireless communications, medical imaging and military applications, just to name a few. Instead of implementing polyphase decomposition, Farrow resampling filter uses low-order polynomials to realize the same functionality, thus results in significant logic savings. It is particularly efficient for processing multiple channels or multiple parallel data paths, where all channels or data paths require the same set of filter coefficients. In this example, we build a Farrow sample rate conversion filter using DSP Builder Advanced Blockset primitive blocks. In particular, we demonstrate how to take advantage of the folding feature of the DSPB-AB. The folding feature of the DSPB-AB automatically realizes resource sharing and hardware re-use based on user specified system parameters. Simulation in Simulink ====================== To run the simulation of the design example in Simulink, perform the following steps: 1. Open the design file farrow.mdl 2. Double click on the Control block on the top design, and uncheck 'Generate Hardware'. We will first do a functional simulation only to verify the algorithm and save on simulation time. We will turn on hardware generation later to generate synthesizable RTL, which takes longer in 9.1 In future release the compile time for generating RTL should be significantly shorter. 3. Double click the Editparam block in top level design and open the setup script setup_farrow.m 4. Review or modify parameters used in the design example 5. To start simulation, select "Start" (Simulation menu) and run the simulation. Make sure the discrete solver is selected with variable simulation steps. Variable simulation step is required by the folding feature. 6. Check the simulation inputs and outputs. The input is a sinusoidal wave, and the output is a decimated or interpolated sinusoidal wave depending on your choice of parameters. The input and output signal spectrums are also presented. Once you are satisfied with the functionality of the algorithm, you can turn on hardward generation in the Control block to generate synthesizable RTL and review resource utilization estimate before you start a Quartus II compilation of your design. To get more details on the design flow using DSP Builder Advanced Blockset, refer to the DSP Builder Advanced Blockset User Guide located at: http://www.altera.com/literature/ug/ug_dsp_builder_adv.pdf Release History =============== Version 9.1 ------------- Initial release Design Examples Disclaimer ========================== These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2006 Altera Corporation. All rights reserved.