Reconfigurable Decimation Filter Design Example v9.1 README File This readme file contains the following sections: o Package Contents o Tool Requirements o General Description o Simulation in Simulink o References o Release History o Design Examples Disclaimer o Contacting Altera Package Contents ================ Altera Variable Rate Decimation Filter v9.1 Design Example Files in this zip download include: o vardownsampler.mdl - DSP Builder Advanced Blockset design file for reconfigurable decimation filter o setup_vardownsampler.m - MATLAB script to configure initialization and parameters of vardownsampler.mdl o vardownsampler_bare.mdl - Design file based on vardownsampler.mdl. Some none-synthesizable test bench blocks are removed for RTL generation Tool Requirements ================= This design example requires the following software package: o Quartus II 9.1SP2 o DSP Builder Advanced Blockset v9.1SP2 o MATLAB/Simulink version R2009a (Design verified in R2009a; DSP Builder Advanced Blockset requires 2007a or later) Please contact your local sales representative if you do not have one of these software tools. General Description ============================= This example demonstrates how to implement a multiple channel variable rate decimation filter in Altera DSP Builder Advanced Blockset. For many medical imaging systems including ultrasound and MRI a re-configurable decimation filter is needed to reduce the echo data sample rate. The input data has a fixed sample rate; however the integer decimation rate needs to be changed real time. Furthermore, the total filter length grows linearly with the decimation rate. Similar requirements may be seen in wireless communications applications and other systems as well. Polyphase structure is highly optimized for this type of applications, because the multiplier count is fixed at compile time and does not grow with rate increase. The key is in the variable length delay taps and efficient filter coefficients storage. This design example has the following key features: • Support arbitrary integer decimation rate (including the cases without rate change), arbitrary number of channels and arbitrary clock rate and input sample rate, as long as the clock rate is high enough to process all channels in a single data path (i.e. no hardware duplication). • Support run-time reconfiguration of decimation rate. • Use of two memory banks for filter coefficients storage instead of pre-storing coefficients for all rates in memory. Update one memory bank while the design is reading coefficients from the other bank. • Real time control of scaling in the FIR data path. Simulation in Simulink ====================== To run the functional simulation of the design example in Simulink, perform the following steps for 9.1 release: 1. Open the design file vardownsampler.mdl 2. Double click on the Control block on the top design, and uncheck 'Generate Hardware'. We will first do a functional simulation only to verify the algorithm and save on simulation time. We will turn on hardware generation later to generate synthesizable RTL. 3. Double click the Editparam block in top level design and open the setup script setup_vardownsampler.m 4. Review or modify parameters used in the design example 5. To start simulation, select "Start" (Simulation menu) and run the simulation. 6. Check the simulation inputs and outputs. The input is a sinusoidal wave, and the output is a decimated sinusoidal wave depending on your choice of parameters. If multiple decimation rate and their cooresponding scaling factors are properly specified in the setup script, you could observe the sample rate change on the output signal in the top level Output Scope. Once you are satisfied with the functionality of the algorithm, you can turn on hardward generation in the Control block of vardownsampler_bare.mdl to generate synthesizable RTL and review resource utilization estimate before you start a Quartus II compilation of your design. The synthesizable part of the two design files are idential with vardownsampler_bare.mdl having some test bench only blocks removed. In future releases you will be able to compile directly vardownsampler.mdl. References ============== 1. DSP Builder Advanced Blockset User Guide http://www.altera.com/literature/ug/ug_dsp_builder_adv.pdf Release History =============== Version 9.1 ------------- Initial release Design Examples Disclaimer ========================== These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2006 Altera Corporation. All rights reserved.