POS-PHY Level 4 (SPI4.2) External PLL Merging Design Example ------------------------------------------------------------ This readme file contains the following sections: • Introduction • Feature Summary • Simulation Instructions • Compilation Instructions • Release History • Design Examples disclaimer • Contacting ALTERA CORPORATION Introduction ------------ This design example demonstrates external PLL sharing between SPI-4.2 transmit and receive core. In the Appendix B of the Altera POS-PHY Level 4 userguide, internal PLL sharing steps has been described. Internal PLL sharing between transmit and receive cores are taken care by Quartus II synthesis tool to merge the PLL during Quartus II compilation. However, in the event where Quartus II compilation fails to merge PLL internally, a possible workaround is to use external PLL merging. For example, when SPI-4.2 transmit and receive cores are implemented in Stratix IV GX ES device, internal PLL merging will not be successful because DPA calibration needs to be enabled in ALTLVDS megafunction to prevent DPA mismatch(refer to Stratix IV GX ES errata). In this circumstance, you will need to use an external PLL to drive the SPI-4.2 transmit and receive core internal logic. For detailed explanation on how to perform external PLL merging between the transmit and receive cores, go to Altera Knowledge Database at: http://www/support/kdb/solutions/rd10152009_939.html The design example has been properly simulated and compiled with Quartus II v9.1. The simulation project folder and Quartus II compiled project is distributed freely together with this README. It is up to the customer to implement it on board that meets the specifications of the design example such that it will work. Customer may modify the design example to meet their design specification. Altera offers no warranty on the design example provided. Feature Summary --------------- This design example runs on EP4SGX230KF40C3ES FPGA and uses 128-bit variations for SPI-4.2 transmit and receive core. When you use external PLL merging between transmit and receive core, please ensure that the SPI-4.2 transmit and receive cores are running at the same LVDS clock frequency and similar data path width variation. This is because a 64-bit variation core will use ½ of the LVDS clock rate while a 128-bit variation core will use ¼ of the LVDS clock rate to clock the internal modules. The design example runs at 1Gbps bandwidth for SPI-4.2 LVDS data packets transfer. Thus, the transmit (tdclk) and receive clock (rdclk) runs at 500 MHz. Status clocks run at 125MHz. The PLL input clock is the SPI-4.2 receive clock (rdclk) that is clocked from an external device. It is important to note that the external SPI-4.2 device needs to clock the PLL and the PLL needs to be locked first before the transmit and receive core can function. The rxsys_clk runs at 250 MHz and is generated by the PLL. Simulation Instructions ----------------------- To run this design example, you need the following software tools: 1. Windows 2000/XP 2. Altera Quartus II v9.1 3. Altera SPI-4.2 transmit core v9.1 4. Altera SPI-4.2 receive core v9. 1 5. Modelsim SE 6.5b or Altera-Modelsim 6.5b To perform the design example simulation, 1. Download the zip package SPI4_External_PLL.zip. 2. Extract the zip package to the path C:\ only. (Note that if you extract to other paths, you to manually modify the DO script for the simulation to work) The steps below describe how to start the Modelsim simulation: 1. Start Modelsim SE 6.5b. 2. Go to File and select Change Directory. Then, select C:\SPI4_External_PLL\simulation\modelsim. 3. After that, point the cursor onto ModelSim> on the transcript console window. Then go to File and choose Load. 4. Select SPI4_External_PLL_run_msim_rtl_verilog.do and hit enter. 5. Done. The Modelsim will compile the SPI_External_PLL_msim_rtl_verilog.do script and generate the simulation waveform. The simulation duration is fixed for 30 us. You can modify the script to adjust the duration of simulation. A pre-saved simulated waveform appears as wave1.do. During simulation, Modelsim will display the signals saved in wave1.do. You can add or remove signals in the waveform window and save it as wave1.do. When SPI4_External_PLL_run_msim_rtl_verilog.do script is re-compiled, the new wave1.do list of signals will appear in the waveform. Compilation Instructions ------------------------ The design example has been pre-compiled. To re-compile the design example, 1. Open Quartus II v9.1 2. Open project SPI4_External_PLL.qar 3. In Task Flow box, double click “Compile ALL” Release History --------------- Version 9.1 – Initial release. Design Example Disclaimer ------------------------- These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Contacting ALTERA CORPORATION ----------------------------- Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2010 Altera Corporation. All rights reserved.