Some Intel FPGA IP cores require purchase of a separate license for production use. The Intel® FPGA IP Evaluation Mode allows you to evaluate these licensed Intel® FPGA IP cores in simulation and hardware, before deciding to purchase a full production IP core license. You can evaluate any of the following with the Intel® FPGA IP Evaluation Mode:
- Simulate the behavior of a licensed IP core in your system.
- Verify the functionality, size, and speed of the IP core quickly and easily.
- Generate time-limited device programming files for designs that include IP cores.
- Program a device with your IP core and verify your design in hardware.
- Tethered—Allows running the design containing the licensed IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel® Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel® Quartus® Prime software, and requires no Intel® Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
- Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel® Quartus® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.
When the evaluation time expires for any licensed IP in the design, the design stops functioning. All IP cores that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.
- To view IP and software license and expiration information, click Tools > License Setup. The License Setup page displays the name,
vendor, version, and license expiration date for the IP cores that you
Figure 2. License Setup Page
- To view the license type for IP cores in your project, run Analysis &
Synthesis, and then view the Synthesis IP Cores
Summary report. This report displays the name, vendor, version,
license type, and other data about the IP cores in your project.
Figure 3. Synthesis IP Cores Summary Report
Intel® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. To obtain your production license keys, visit the Self-Service Licensing Center or contact your local Intel FPGA representative.
The Intel® FPGA Software License Agreements governs the installation and use of licensed IP cores and the Intel® Quartus® Prime design software and all unlicensed IP cores.
Specify either an active_high or active_low polarity of the time-out signal (ip_timeout) with the timeout_indicator parameter.
Timeout Indicator VHDL Component Declaration
component ocp_timeout_indicator is generic ( TIMEOUT_INDICATOR: string := "ACTIVE_HIGH" ); port ( ip_timeout: out std_logic ); end component ocp_timeout_indicator;
Timeout Indicator VHDL Instantiation Prototype
My_Instance : ocp_timeout_indicator GENERIC MAP(TIMEOUT_INDICATOR => "ACTIVE_HIGH") PORT MAP(ip_timeout => My_Output);
Timeout Indicator Verilog HDL Instantiation Prototype
ocp_timeout_indicator my_instance (.ip_timeout(my_output)); defparam my_instance.TIMEOUT_INDICATOR = "ACTIVE_HIGH";
- In the Intel® Quartus® Prime software, click Assignments > Settings > Compilation Process Settings.
- Click the More Settings button.
For OpenCore Plus hardware
evaluation, select Disable.
Figure 6. Disable IP Evaluation Mode
The most flexible methodology for distributed work flows is for every designer to have a production license for all IP included in their portion of the design. However, you can use the Intel® Quartus® Prime Standard Edition incremental compilation feature to temporarily avoid the licensing requirement by following these steps on any machine with an Intel® Quartus® Prime Standard Edition license:
Click Assignments > Settings > Compilation Process Settings > More Settings, and disable OpenCore plus hardware
Note: You cannot use incremental compilation to compile a portion of your design that contains licensed IP in evaluation mode, and then import that design as a pre-compiled module to another machine that has a production license for the IP.
- To compile the design, click Processing > Start Compilation.
- To export the compilation results as a design partition, click Project > Export Design Partition. The Intel® Quartus® Prime software generates an Intel® Quartus® Prime Exported Partition File (.qxp) in the project directory.
- To generate a full production, non-time-limited device programming file for the exported partition, you must import the partition to a project with access to a full production license for all licensed IP core in the design. Click Project > Import Design Partitions to import a design partition.
|Added section on IP evaluation in teams.|
|2007.09.15||Removed references to unsupported LogicLock® flow.|
|2007.05.08||Updated steps for disabling evaluation mode.|
|2003.10.15||Initial document release.|