These guidelines facilitate board designs for the Intel® FPGA HDMI IP video interfaces.
The TMDS channels carry video, audio, and auxiliary data. The DDC is based on I2C protocol. The Intel® FPGA HDMI IP core uses the DDC to read Extended Display Identification Data (EDID) and exchange configuration and status information between an HDMI source and sink.
- Use no more than two vias per trace and avoid via stubs
- Match the differential pair impedance to the impedance of the connector and cable assembly (100 ohm ±10%)
- Minimize inter-pair and intra-pair skew to meet the TMDS signal skew requirement
- Avoid routing a differential pair over a gap in the underneath plane
- Use standard high speed PCB design practices
To interface with an FPGA, you need to translate the 5V HPD signal to the FPGA I/O voltage level (VCCIO), using a voltage level translator such as TI TXB0102, which does not have pull-up resistors integrated. An HDMI source needs to pull down the HPD signal so that it can reliably differentiate between a floating HPD signal and a high voltage level HPD signal.
An HDMI sink +5V Power signal must be translated to FPGA I/O voltage level (VCCIO). The signal must be weakly pulled down with a resistor (10K) to differentiate a floating +5V Power signal when not driven by an HDMI source. An HDMI source +5V Power signal has over-current protection of no more than 0.5A.
To interface with an Intel FPGA, you need to translate the 5V SCL and SDA signal level to the FPGA I/O voltage level (VCCIO) using a voltage level translator.
|January 2018||2018.01.22||Initial release.
Note: This document contains Intel® FPGA HDMI design guidelines that were removed from AN 745: Design Guidelines for DisplayPort and HDMI Interfaces and renamed AN 745: Design Guidelines for Intel® FPGA DisplayPort Interface.