The JESD204B standard provides a serial data link interface between converters and FPGAs. The JESD204B MegaCore function intellectual property (IP) for Altera® FPGAs allows you to transmit and receive data on the FPGA fabric interface by utilizing the Avalon-Streaming (Avalon-ST) source and sink interfaces, with unidirectional flow of data. The JESD204B MegaCore function has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) device.
This reference design highlights the performance and interoperability of the JESD204B MegaCore function. The design uses an Arria® V GT FPGA Development Kit as well as the Analog Devices Inc. (ADI) AD9250 converter daughter card (evaluation module) connected to the development board.
The system-level diagram shows how the different modules connect in this reference design.
In this setup where LMF = 222, the data rate of the both transceiver lanes is 4.915 Gbps. The AD9517 clock generator provides 122.88 MHz clock to the FPGA and 245.76 MHz sampling clock to both AD9250 devices. The transceiver CDR PLL input reference clock (pll_ref_clk) uses the FPGA clock to generate the frame clock and link clock.
The reference design consists of the following modules:
- JESD204B MegaCore function
- Duplex JESD204B MegaCore function
- TX & RX transport layer
- core PLL
- transceiver reconfiguration controller
- transceiver reset controllers
- control unit
- SPI master
- SYSREF generator
- In-System Sources and Probes (ISSP)
- Qsys System
The design example also contains a parallel pseudorandom-binary-sequence (PRBS) data generator and checker. The data generator generates a PRBS9 data pattern and the data checker verifies the PRBS9 data received. The checker flags an error when it finds a mismatch of data sample. You can monitor the data checker's error flag using the status LED on the development board or the Signal Tap II Logic Analyzer tool.
The reference design implements the JESD204B MegaCore function with the following parameter configuration.
|L||2||Number of lanes per converter device|
|M||2||Number of converters per device|
|F||2||Number of octets per frame|
|S||1||Number of transmitted samples per converter per frame|
|N||14||Number of conversion bits per converter|
|N'||16||Number of transmitted bits per sample (JESD204 word size, which is in nibble group)|
|K||32||Number of frames per multiframe|
|CS||0||Number of control bits per conversion sample|
|CF||0||Number of control words per frame clock period per link|
|HD||0||High Density user data format|
|FRAMECLK_DIV||1||The divider ratio of the frame_clk|
You need to configure both the AD9517 clock generator and AD9250 ADC module for normal operation. Between the FPGA and CPLD (on the AD9250 module), a 4-wire SPI configures the clock generator and ADC. The CPLD, which acts as an SPI slave, uses the first 8-bits of the 32-bits SPI transaction as the preselection bits to configure the clock generator, converter 1 (ADC #1), or converter 2 (ADC #2). The remaining 24-bits follow the SPI interface timing requirements as listed in the AD9517 and AD9250 datasheet.
The FPGA, which acts as an SPI master, writes the SPI instruction and register data following the sequence and content in ROM-1 port of the memory initialization file (MIF). Figure shows a timing diagram for the correlation between the bit settings in MIF and the write instruction.
The generator generates the pulses with a frequency of (4 × link clock) / (F × K).
The ISSP is instantiated to control the global reset and to enable serial loopback.
Global reset. Assert high to reset and low to release the reset.
Enables the serial loopback of the transceiver channel. Assert high to enable or low to disable the serial loopback feature.
Follow the steps below to examine the Qsys system:
- Launch the Quartus II software.
- On the File menu, click Open.
- Browse and select the jesd204b_avmm_interface.qsys file located in the project directory.
- Click Open.
The Qsys system consists of the following components:
- JTAG to Avalon Master Bridge—acts as the Avalon-MM master in the reference design, This component is the main communication channel between the System Console tool and the Avalon-MM slave translator in the design. The System Console tool accesses the RX registers of the JESD204B MegaCore function.
- Avalon-MM Slave Translator—exports all required Avalon signals to the top-level design. With the Avalon signals exported, the Qsys system can interface with any Avalon-compliant component that resides outside of the Qsys component library.
Avalon-MM Slave Translator
Exports Avalon-MM signals to interface with the JESD204B MegaCore function.
|altera_jesd204||JESD204B MegaCore function configured in duplex mode.|
|issp||Signal source and probe module.|
|jesd204b_avmm_interface||Qsys Avalon-MM component for interfacing between the JESD204B MegaCore function and System Console.|
|pattern||PRBS data generator and checker module.|
|spi||SPI master module.|
|transport_layer||Transport layer assembler (TX) and deassembler (RX) module.|
|xcvr_reset_control_module||Transceiver reset controller module.|
- Read the MIF content from the FPGA ROM.
- Configure AD9517 clock generator.
- Configure ADC #2.
- Deassert the Avalon-MM reset after the transceiver is out of reset.
- Deassert the link and frame reset.
- Link layer state machine goes through code group synchronization (CGS), initial lane synchronization (ILAS), and user data phase.
- Upon successfully entering the user data phase, the PRBS checker is enabled.
The reference design requires the following hardware and software tools:
- Arria V GT FPGA Development Kit with 19 V power adaptor
- ADI AD9250 Rapid Development Board (AD-FMCJESDADC1-EBZ)
- Mini-USB cable
- Quartus®II software
- The AD9250 module derives power from the FMC connector on the development board.
- The AD9250 module supplies the device clock to FPGA 2.
- For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the AD9250 module.
To set up the board connections, perform the following steps:
- Install the ADI AD9250 daughter card module to the FMC port (J9) on the development board as shown in figure.
- Connect the mini-USB cable to the mini USB connector (J7) on development board.
- Connect the power adapter shipped with the development board to the power supply jack (J6).
Turn on the
You are now ready to download the .sof file and program the FPGA device on the development board.
|Top Level Signal Name||FPGA 2 Pin Number||I/O Standard||Direction|
|LED Board Reference||Signal Name||Description|
|D26||data_error [1:0]||Single AND-ed error status signal for the PRBS checkers from both lane 0 & lane 1. The LED illuminates to indicate a data error.|
|D27||jesd204_tx_int||Link layer TX interrupt signal. Applicable only when internal serial loopback is enabled. The LED illuminates to indicate a TX interrupt.|
|D28||jesd204_rx_int||Link layer RX interrupt signal. The LED illuminates to indicate a RX interrupt.|
|D29||rx_dev_sync_n||SYNC~ signal to the transmitter. The LED illuminates to indicate that the transmitter has received K28.5 characters.|
|D30||dev_lane_aligned||RX path lane alignment status signal for the device. The LED illuminates to indicate that lane alignment is achieved.|
|D31||avs_rst_n||Link layer CSR Avalon-MM reset signal. The LED illuminates to indicate that the Avalon-MM interface is out of reset.|
|D32||link_rst_n||Link layer reset signal. The LED illuminates to indicate that the link layer is out of reset.|
|D33||frame_rst_n||Transport layer reset signal. The LED illuminates to indicate that the transport layer is out of reset.|
- Extract the reference design's archive file from avgt_jesd204b_ad9250_ed.zip.
- Launch the Quartus II software.
- On the File menu, click Open.
- Navigate to your project directory and select the avgt_jesd204b_ad9250_ed_<Quartus II version>.qar file. Click Open.
- In the Restore Archived Project window, set the archive file name and destination folder. Click OK.
To download the
.sof file and program the FPGA device on the development
board, perform the following steps:
- On the Tools menu, click Programmer.
- Click Add File.
- Navigate to <project directory> \<output_files>\jesd204b_ed_golden.sof and click Open.
- Click Start to download the file into the FPGA device on the development board.
Use the System
Console tool to reset the system and trigger an initialization for the JESD204B
MegaCore function link.
Optionally, if you want to edit the JESD204B MegaCore function parameters and recompile the reference design, refer to the section on section.
With the Avalon to JTAG Master Bridge, the System Console tool can access the RX registers of the JESD204B MegaCore function. The System Console tool issues commands to reset and initiate the JESD204B MegaCore function link in the reference design.
This design example uses a Tcl script called main.tcl that consists of several different procedures with different functionality.
To launch the System Console, perform the following steps:
- Launch the Quartus II software.
- On the Tools menu, select System Console and click System Console.
- Ensure that the present working directory contains main.tcl
The following table lists the procedures in main.tcl. You can type in a procedure name and its value to execute the commands.
|read_rxstatus3||Read JESD204 RX status 3 register (read back
data in hexadecimal value). This signal is asserted to indicate:
|read_rxstatus4||Read JESD204 RX status 4 register (read back data in hexadecimal value). This signal is asserted to indicate the current state of RX DLL code group synchronization state machine for each lane.|
|read_rxstatus5||Read JESD204 RX status 5 register (read back data in hexadecimal value). This signal is asserted to indicate the current state of RX DLL frame synchronization state machine for each lane.|
|read_rxstatus7||Read JESD204 RX status 7 register (read back data in hexadecimal value). This signal is asserted to indicate the status of RX DLL user data phase for each lane.|
|read_ilas_octet0||Read ILAS octet 0 register (read back data in hexadecimal value). This signal links the control configuration fields in octets for configuration checking.|
|read_ilas_octet1||Read ILAS octet 1 register (read back data in hexadecimal value). This signal links the control configuration fields in octets for configuration checking.|
|read_ilas_octet2||Read ILAS octet 2 register (read back data in hexadecimal value). This signal links the control configuration fields in octets for configuration checking.|
|read_ilas_octet3||Read ILAS octet 3 register (read back data in hexadecimal value). This signal links the control configuration fields in octets for configuration checking.|
|read_rx_err0||Read JESD204 RX error status 0 register (read back data in hexadecimal value). This signal indicates the error status in the MegaCore's RX path.|
|read_rx_err1||Read JESD204 RX error status 1 register (read back data in hexadecimal value). This signal indicates the error status in the MegaCore's RX path.|
|sloopback 1||Enable serial loopback.|
|sloopback 0||Disable serial loopback.|
The following example shows the execution of the above commands in the Tcl Console.
source main.tcl sloopback 0 >> Disable serial loopback reset >> Reset the whole reference design system after disabling serial loopback >> Reset Done! read_rxstatus3 >> Performing a read on rxstatus3 register... >> The rxstatus3 is 0x00000003 >> Info: Closed JTAG Master Service read_rxstatus4 >> Performing a read on rxstatus4 register... >> The rxstatus4 is 0x0000000a >> Info: Closed JTAG Master Service read_rxstatus5 >> Performing a read on rxstatus5 register... >> The rxstatus5 is 0x0000000a >> Info: Closed JTAG Master Service read_rxstatus7 >> Performing a read on rxstatus7 register... >> The rxstatus7 is 0x00030003 >> Info: Closed JTAG Master Service read_ilas_octet0 >> Performing a read on ilas_octet0 register... >> The ilas_octet0 is 0x810000b9 >> Info: Closed JTAG Master Service read_ilas_octet1 >> Performing a read on ilas_octet1 register... >> The ilas_octet1 is 0x0d011f01 >> Info: Closed JTAG Master Service read_ilas_octet2 >> Performing a read on ilas_octet2 register... >> The ilas_octet2 is 0x0000202f >> Info: Closed JTAG Master Service read_ilas_octet3 >> Performing a read on ilas_octet3 register... >> The ilas_octet3 is 0x0000fa00 >> Info: Closed JTAG Master Service read_rx_err0 >> Performing a read on rx_err0 register... >> The rx_err0 is 0x00000000 >> Info: Closed JTAG Master Service read_rx_err1 >> Performing a read on rx_err1 register... >> The rx_err1 is 0x00000000 >> Info: Closed JTAG Master Service
These commands allow the System Console to communicate directly with the JESD204B MegaCore function via the Avalon to JTAG Bridge Master.
Upon device power up, assert reset using Tcl command in the System Console tool to trigger an initialization for the JESD204B MegaCore function link in the reference design.
The following list describes the link initialization sequence.
|1||The input of the link layer or the output of the PCS (jesd204_rx_pcs_data[63:0]) receives 0xBC or K28.5 (/K/) characters.||Check both the lane1_cs_state and lane0_cs_state register identifiers by executing read_rxstatus4 command in the System Console tool to read the JESD204 RX status register.||0x02 is asserted at both lane1_cs_state[3:2] for lane 1 and lane0_cs_state[1:0] for lane 0, which indicates that code group synchronization (CGS) phase is detected. The receiver deasserts the synchronization request signal upon receiving four consecutive K28.5 characters. Then, the rx_dev_sync_n signal will be deasserted.|
|2||When 0x1C or K28.0 (/R/) character is received, the ILAS phase is detected.||Check both the lane1_cs_state and lane0_cs_state register identifiers by executing read_rxstatus5 command in the System Console tool to read the JESD204 RX status register.||0x02 is asserted at both lane1_cs_state[3:2] for lane 1 and lane0_cs_state[1:0] for lane 0. The ILAS consists of four multiframes. The 1st, 3rd, and 4th multiframes begin with /R/ character and end with 0x7C or K28.3 (/A/) character. On the 2nd multiframe, the ADC transmits the JESD204B link configuration information to the receiver. The 2nd multiframe begins with /R/ character, followed by 0x9C or K28.4 (/Q/) character and ends with /A/ character.|
|3||User data phase enters after four multiframes of ILAS.||Check both the lane1_dll_user_data_phase and lane0_dll_user_data_phase register identifiers by executing read_rxstatus7 command in the System Console tool to read the JESD204 RX status register.||Both lane1_dll_user_data_phase1 of lane 1 & lane0_dll_user_data_phase0 of lane 0 are asserted. In this phase, the ADC transmits PRBS data to the FPGA.|
|4||All lanes are aligned, indicated by the assertion of the dev_lane_aligned signal.||The link layer begins transmitting data to the transport layer.||LED D29 illuminates to indicate that lane alignment is achieved.|
|5||Link initialization successful. Monitor the data integrity through the PRBS checker.||The PRBS checker receives data from the transport layer and checks the received data against the internally generated PRBS polynomial data. The polynomial length and feedback tap position must be the same for both the ADC PRBS generator and the FPGA PRBS checker. The AD9250 module is set to output PRBS-9 data, with feedback tap of 5.||
This section describes some editable parameters when interoperating with the AD9250 module. When you make modification to the JESD204B MegaCore function in the Quartus II software, you must make corresponding changes to the AD9250 configuration file.
The example below demonstrates the following parameter modification:
- Subclass 1 to 0
- K from 32 to 16
- Disable the scrambler
To edit the JESD204B MegaCore function parameters and recompile the reference design, perform the following steps:
On the Tools menu,
MegaWizard Plug-In Manager.
- Select Edit an existing custom megafunction variation, then click Next.
Select the existing
megafunction variation file (.v/.vhd/.vhdl) for the altera_jesd204
component, then click
Edit the MegaCore
parameters, then click
Finish to close the parameter editor and generate the
jesd204b_ed_top.v file and change the
localparam K value from 32 to 16.
Use the text editor
to change the following bit settings in the AD9250 module configuration file
located in the
• At content line 22, change register 0x6E bit from 1 to 0 to disable scrambling: 10000001000000000110111000000001; • At content line 23, change register 0x70 bit from 1 to 0 to set K = 16 (0x0F + 1): 10000001000000000111000000001111; • At content line 25, change register 0x73 bit from 1 to 0 for subclass 0: 10000001000000000111001100001111; • At content line 26, change register 0x3A bit [2:0] from “111” to “000” to turn off SYSREF detection: 10000001000000000011101000000000;
Optionally, if you
want to rename the MIF, change the pointer to the MIF located in
rom_1port #( .INIT_FILE ("./control_unit/<renamed MIF file>.mif"), ) u_rom0 ( .clock (clk), .clken (rom_clken), .address (rom_addr_ptr), .q (rom0_data_out) );
On the Processing
|May 2015||2015.05.11||Revised the name of ADI AD9250 evaluation module (EVM) to ADI AD9250 Rapid Development Board.|
|December 2013||2013.12.02||Initial release.|