Intel FPGA Triple-Speed Ethernet IP Core User Guide
About This IP Core
It incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os. When offered in MAC-only mode, the IP connects with an external PHY chip using MII, GMII, or RGMII interface. The IP core was tested and successfully validated by the University of New Hampshire (UNH) interoperability lab.
Device Family Support
The IP core provides the following support for Intel® FPGA device families.
Device Support Level | Definition |
---|---|
Preliminary | Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. This IP core can be used in production designs with caution. |
Final | Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. This IP core is ready to be used in production designs. |
Device Family | Support | Minimum Speed Grade
with 1588 Feature |
---|---|---|
Intel® Stratix® 10 | Preliminary | -I3 |
Stratix® V | Final | -I3 |
Stratix® IV | Final | Not supported |
Intel® Arria® 10 | Final | -I3 |
Arria® V | Final | -I5 |
Arria® II | Final | Not supported |
Intel® Cyclone® 10 GX | Final | -I3 |
Intel® Cyclone® 10 LP | Final | Not supported |
Cyclone® V | Final | -I7 |
Cyclone® IV | Final | Not supported |
Intel® MAX® 10 | Final | -I7 |
Features
- Complete triple-speed Ethernet IP: 10/100/1000-Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA.
- Successful validation from the University of New Hampshire (UNH) InterOperability Lab.
- 10/100/1000-Mbps Ethernet MAC features:
- Multiple variations: 10/100/1000-Mbps Ethernet MAC in full duplex, 10/100-Mbps Ethernet MAC in half duplex, 10/100-Mbps or 1000-Mbps small MAC (resource-efficient variant), and multiport MAC that supports up to 24 ports.
- Support for basic, VLAN, stacked VLAN, and jumbo Ethernet frames. Also supports control frames including pause frames.
- Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.
- Optional statistics counters.
- MAC interfaces:
- Client side—8-bit or 32-bit Avalon® Streaming (Avalon-ST)
- Network side—medium independent interface (MII), gigabit medium independent interface (GMII), or reduced gigabit medium independent interface (RGMII) on the network side. Optional loopback on these interfaces.
- Optional management data I/O (MDIO) master interface for PHY device management.
- 1000BASE-X/SGMII PCS features:
- Compliance with Clause 36 of the IEEE standard 802.3.
- Optional embedded PMA implemented with serial transceiver or LVDS I/O and soft CDR in Intel FPGA devices that support this interface at 1.25-Gbps data rate.
- Support for auto-negotiation as defined in Clause 37.
- Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and 1000BASE-T PHYs if the PHYs support SGMII.
- PCS interfaces:
- Client side—MII or GMII
- Network side—ten-bit interface (TBI) for PCS without PMA; 1.25-Gbps serial interface for PCS with PMA implemented with serial transceiver or LVDS I/O and soft CDR in Intel FPGA devices that support this interface at 1.25-Gbps data rate.
- Programmable features via 32-bit
configuration registers:
- FIFO buffer thresholds.
- Pause quanta for flow control.
- Source and destination MAC addresses.
- Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.
- Promiscuous mode—receive frame filtering is disabled in this mode.
- Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants containing 1000BASE-X/SGMII PCS (with or without MAC), the frame length is up to 10 Kbytes.
- Optional auto-negotiation for the 1000BASE-X/SGMII PCS.
- Error correction code protection feature for internal memory blocks.
- Optional IEEE 1588v2 feature for 10/100/1000-Mbps Ethernet MAC with SGMII PCS and embedded serial PMA variation operating without internal FIFO buffer in full-duplex mode, 10/100/1000-Mbps MAC with SGMII PCS and embedded LVDS I/O, or MAC only variation operating without internal FIFO buffer in full-duplex mode. These features are supported in Intel® Stratix® 10, Arria® V, Intel® Arria® 10, Intel® Cyclone® 10 GX, Cyclone® V, Intel® MAX® 10, and Stratix® V device families.
10/100/1000 Ethernet MAC Versus Small MAC
Feature | 10/100/1000 Ethernet MAC | Small MAC |
---|---|---|
Speed | Triple speed (10/100/1000 Mbps) | 10/100 Mbps or 1000 Mbps |
External interfaces | MII/GMII or RGMII | MII only for 10/100 Mbps small MAC, GMII or RGMII for 1000 Mbps small MAC |
Control interface registers | Fully programmable | Limited programmable
options. The following options are fixed:
|
Synthesis options | Fully configurable | Limited configurable
options. The following options are NOT available:
|
High-Level Block Diagrams
Example Applications
The 10/100/1000-Gbps Ethernet MAC only variation can serve as a bridge between the user application and standard fast or gigabit Ethernet PHY devices.
When configured to include the 1000BASE-X/SGMII PCS function, the IP core can seamlessly connect to any industry standard gigabit Ethernet PHY device via a TBI. Alternatively, when the 1000BASE-X/SGMII PCS function is configured to include an embedded PMA, the IP core can connect directly to a gigabit interface converter (GBIC), small form-factor pluggable (SFP) module, or an SGMII PHY.
IP Core Verification
Intel used a highly parameterizeable transaction-based testbench to test the following aspects of the IP core:
- Register access
- MDIO access
- Frame transmission and error handling
- Frame reception and error handling
- Ethernet frame MAC address filtering
- Flow control
- Retransmission in half-duplex
Intel has also validated the Triple-Speed Ethernet IP core in both optical and copper platforms using the following development kits:
- Nios® II Development Kit, Cyclone® II Edition (2C35)
- Intel® Arria® 10 FPGA Development Kit
- Intel® Cyclone® 10 LP FPGA Development Kit
- Stratix® III FPGA Development Kit
- Stratix® IV FPGA Development Kit
- Stratix® V FPGA Development Kit
- Intel® Stratix® 10 FPGA Development Kit
- Quad 10/100/1000 Marvell PHY
- MorethanIP 10/100 and 10/100/1000 Ethernet PHY Daughtercards
Optical Platform
The FPGA application implements the Ethernet MAC, the 1000BASE-X PCS, and an internal system using Ethernet connectivity. This internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an optical module is provided through an external SFP optical module. Certified 1.25 GBaud optical SFP transceivers are Finisar 1000BASE-SX FTLF8519P2BNL, Finisar 1000BASE-LX FTRJ-1319-3, and Avago Technologies AFBR-5710Z.
Copper Platform
A 10/100/1000 Mbps Ethernet MAC and an internal system are implemented in the FPGA. The internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an Ethernet link is provided through a combined MII to an external PHY module. Certified 1.25 GBaud copper SFP transceivers are Finisar FCMJ-8521-3, Methode DM7041, and Avago Technologies ABCU-5700RZ.
Performance and Resource Utilization
IP Core | Settings | FIFO Buffer Size (Bits) | Combinational ALUTs | Logic Registers | Memory
(M20K) |
---|---|---|---|---|---|
10/100/1000-Mbps Ethernet MAC |
MII/GMII. All MAC options enabled. Full- and half-duplex. |
2048x32 | 3643 | 5203 | 16 |
2048x8 | 3496 | 5105 | 11 | ||
10/100-Mbps Small MAC |
MII. Full- and half-duplex. |
2048x32 | 1501 | 2226 | 12 |
1000BASE-X/SGMII PCS |
SGMII bridge enabled. |
– | 838 | 1188 | 2 |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). |
– | 759 | 1001 | 4 | |
1000BASE-X. |
– | 869 | 1238 | 0 |
IP Core | Settings | FIFO Buffer Size (Bits) | Combinational ALUTs | Logic Registers | Memory
(M9K Blocks/ M144K Blocks/MLAB Bits) |
---|---|---|---|---|---|
10/100/1000-Mbps Ethernet MAC |
RGMII. All MAC options enabled. Full- and half-duplex. |
2048x32 | 3357 | 3947 | 26/0/1828 |
1000BASE-X/SGMII PCS | 1000BASE-X. | – | 624 | 661 | 0/0/0 |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). |
– | 1191 | 1214 | 1/0/160 |
IP Core | Settings | FIFO Buffer Size (Bits) | Combinational ALUTs | Logic Registers | Memory
(M20K) |
---|---|---|---|---|---|
10/100/1000-Mbps Ethernet MAC |
MII/GMII. All MAC options enabled. Full- and half-duplex. |
2048x32 | 3858 | 5325 | 16 |
2048x8 | 3666 | 5125 | 11 | ||
10/100-Mbps Small MAC |
MII. Full- and half-duplex. |
2048x32 | 1441 | 2126 | 12 |
1000-Mbps Small MAC |
GMII. Full-duplex only. |
2048x32 | 1152 | 1894 | 10 |
1000BASE-X/SGMII PCS |
SGMII bridge enabled. |
– | 851 | 1187 | 2 |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). |
– | 658 | 1006 | 2 | |
1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO). |
– | 658 | 1371 | 2 |
IP Core | Settings | FIFO Buffer Size (Bits) | Combinational ALUTs | Logic Registers | Memory
(M9K) |
---|---|---|---|---|---|
10/100/1000-Mbps Ethernet MAC |
MII/GMII. All MAC options enabled. Full- and half-duplex. |
2048x8 | 6724 | 4840 | 17 |
– | 5863 | 4204 | 8 | ||
1000BASE-X/SGMII PCS |
1000BASE-X. SGMII bridge enabled. |
– | 1628 | 1133 | 2 |
10/100-Mbps Small MAC |
MII. Full and half-duplex only. |
– | 2416 | 1933 | 24 |
1000-Mbps Small MAC |
GMII. Full-duplex only. |
– | 1998 | 1645 | 24 |
IP Core | Settings | FIFO Buffer Size (Bits) | Logic Elements | Logic Registers | Memory
(M10K) |
---|---|---|---|---|---|
10/100/1000-Mbps Ethernet MAC |
MII/GMII. Full- and half-duplex. |
2048x32 | 3644 | 5340 | 27 |
2048x8 | 3489 | 5185 | 15 | ||
10/100-Mbps Small MAC |
MII. Full- and half-duplex. |
2048x32 | 1539 | 2295 | 21 |
1000-Mbps Small MAC |
RGMII. Full-duplex only. |
2048x32 | 1265 | 2060 | 20 |
1000BASE-X/SGMII PCS |
SGMII bridge enabled |
– | 844 | 1241 | 2 |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). |
– | 656 | 947 | 9 | |
1000BASE-X. SGMII bridge enabled. |
– | 836 | 1097 | 9 |
IP Core | Settings | FIFO Buffer Size (Bits) | Logic Elements | Logic Registers | Memory
(M9K Blocks/ M144K Blocks/ MLAB Bits) |
---|---|---|---|---|---|
1000-Mbps Small MAC |
RGMII Full-duplex only. |
2048x32 | 2161 | 1699 | 24/0/0 |
10/100/1000-Mbps Ethernet MAC |
MII/GMII Full- and half-duplex. |
2048x32 | 5614 | 3666 | 31/0/0 |
1000BASE-X/SGMII PCS | 1000BASE-X. | – | 1149 | 661 | 0/0/0 |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). |
– | 2001 | 1127 | 2/0/0 |
IP Core | Settings | FIFO Buffer Size (Bits) | Logic Elements | Logic Registers | Memory
(M9K) |
---|---|---|---|---|---|
10/100/1000-Mbps Ethernet MAC |
MII/GMII. Full- and half-duplex. |
2048x32 | 6806 | 4943 | 30 |
2048x8 | 6593 | 4767 | 17 | ||
10/100-Mbps Small MAC |
MII. Full- and half-duplex. |
2048x32 | 2650 | 2117 | 24 |
1000-Mbps Small MAC |
RGMII Full-duplex only. |
2048x32 | 2286 | 1862 | 24 |
IP Core | Settings | FIFO Buffer Size (Bits) | Combinational ALUTs | Logic Registers | Memory
(M20K) |
---|---|---|---|---|---|
10/100/1000-Mbps Ethernet MAC |
MII/GMII. All MAC options enabled. Full- and half-duplex. |
2048x32 | 3858 | 5325 | 16 |
2048x8 | 3666 | 5125 | 11 | ||
10/100-Mbps Small MAC |
MII. Full-duplex only. |
2048x32 | 1283 | 2131 | 10 |
1000-Mbps Small MAC |
GMII. Full-duplex only. |
2048x32 | 1251 | 2112 | 10 |
1000BASE-X/SGMII PCS |
SGMII bridge enabled. |
– | 907 | 1378 | 2 |
1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO). |
– | 925 | 1485 | 2 |
IP Core | Settings | FIFO Buffer Size (Bits) | Combinational ALUTs | Logic Registers | Memory
(M20K Blocks/ MLAB Bits) |
---|---|---|---|---|---|
10/100-Mbps Small MAC |
MII. Full- and half-duplex. |
2048x32 | 1261 | 2018 | 11/0 |
MII. All MAC options enabled. |
2048x32 | 1261 | 2018 | 11/0 | |
1000-Mbps Small MAC |
GMII. All MAC options enabled. |
2048x32 | 1227 | 1959 | 10/128 |
RGMII. All MAC options enabled. |
2048x32 | 1237 | 1984 | 10/128 | |
10/100/1000-Mbps Ethernet MAC |
MII/GMII. Full- and half-duplex. |
— | 3137 | 4298 | 5/2048 |
2048x8 | 3627 | 4971 | 10/2048 | ||
2048x32 | 3777 | 5145 | 16/2048 | ||
MII/GMII. All MAC options enabled. |
2048x32 | 3454 | 4928 | 16/768 | |
RGMII. All MAC options enabled. |
2048x32 | 3466 | 4933 | 16/768 | |
1000BASE-X/SGMII PCS | 1000BASE-X. | – | 614 | 786 | 0/0 |
1000BASE-X. SGMII bridge enabled. |
– | 839 | 1160 | 0/480 | |
1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO). |
– | 857 | 1250 | 0/480 | |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). |
– | 2203 | 1991 | 5/2208 | |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). The reconfig controller is compiled with this variation. |
– | 1441 | 903 | 4/2048 | |
10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS |
All MAC options enabled. SGMII bridge enabled. |
2048×32 | 4306 | 6132 | 16/1248 |
Default MAC options. SGMII bridge enabled. IEEE 1588v2 feature enabled. |
0 | 5062 | 5318 | 4/1536 |
IP Core | Settings | FIFO Buffer Size (Bits) | Combinational ALUTs | Logic Registers | Memory
(M9K Blocks/ M144K Blocks/MLAB Bits) |
---|---|---|---|---|---|
10/100-Mbps Small MAC |
MII. Full- and half-duplex. |
2048x32 | 1410 | 2127 | 12/1/1408 |
MII. All MAC options enabled. |
2048x32 | 1157 | 1894 | 12/1/128 | |
1000-Mbps Small MAC |
GMII. All MAC options enabled. |
2048x32 | 1160 | 1827 | 12/1/176 |
RGMII. All MAC options enabled. |
2048x32 | 1170 | 1861 | 12/1/176 | |
10/100/1000-Mbps Ethernet MAC |
MII/GMII. Full- and half-duplex. |
– | 2721 | 3395 | 0/0/3364 |
2048x8 | 3201 | 3977 | 8/0/3620 | ||
2048x32 | 3345 | 4425 | 12/1/3364 | ||
MII/GMII. All MAC options enabled. |
2048x32 | 3125 | 3994 | 12/1/2084 | |
RGMII. All MAC options enabled. |
2048x32 | 3133 | 4021 | 12/1/2084 | |
1000BASE-X/SGMII PCS | 1000BASE-X. | – | 624 | 661 | 0/0/0 |
1000BASE-X. SGMII bridge enabled. |
– | 808 | 986 | 2/0/0 | |
1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO). |
– | 819 | 1057 | 2/0/0 | |
1000BASE-X. SGMII bridge enabled. PMA block (GXB). |
– | 1189 | 1212 | 1/0/160 | |
10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS |
All MAC options enabled. SGMII bridge enabled. |
2048×32 | 3971 | 4950 | 14/1/2084 |
Release Information
Item | Description |
---|---|
Version | 17.1 |
Release Date | November 2017 |
Ordering Code |
Triple-Speed Ethernet: IP-TRIETHERNET
IEEE 1588v2 for Triple-Speed Ethernet: IP-TRIETHERNETF |
Product ID(s) |
Triple-Speed Ethernet: 00BD
IEEE 1588v2 for Triple-Speed Ethernet: 0104 |
Vendor ID(s) | 6AF7 |
Intel verifies that the current version of the Intel® Quartus® Prime software compiles the previous version of each IP core. The Intel FPGA IP Release Notes report any exceptions to this verification. Intel does not verify compilation with IP core versions older than one release.
Getting Started with Intel FPGA IP Cores
Intel and strategic IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for Intel FPGA devices. The Intel® Quartus® Prime software installation includes the Intel FPGA IP library.
For more information on how to install and use Intel FPGA IP Cores, refer to the Introduction to Intel FPGA IP Cores.
Design Walkthrough
This walkthrough explains how to create a Triple-Speed Ethernet IP core design using Platform Designer in the Intel® Quartus® Prime software. After you generate a custom variation of the Triple-Speed Ethernet IP core, you can incorporate it into your overall project.
This walkthrough includes the following steps:
Creating a New Intel Quartus Prime Project
You need to create a new Intel® Quartus® Prime project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity.
To create a new project, follow these steps:
- Launch the Intel® Quartus® Prime software on your PC. Alternatively, you can use the Intel® Quartus® Prime Lite Edition software.
- On the File menu, click New Project Wizard.
- In the New Project Wizard: Directory, Name, Top-Level Entity page, specify the working directory, project name, and top-level design entity name. Click Next.
- In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include in the project.1 Click Next.
- In the New Project Wizard: Family & Device Settings page, select the device family and specific device you want to target for compilation. Click Next.
- In the EDA Tool Settings page, select the EDA tools you want to use with the Intel® Quartus® Prime software to develop your project.
- The last page in the New Project Wizard window shows the summary of your chosen settings. Click Finish to complete the Intel® Quartus® Prime project creation.
Generating a Design Example or Simulation Model
In the parameter editor, click Example Design to create a functional simulation model (design example that includes a testbench). The testbench and the automated script are located in the <variation name>_testbench directory.
You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.
Simulate the System
Compiling the Triple-Speed Ethernet IP Core Design
Refer to Design Considerations chapter before compiling the Triple-Speed Ethernet IP core design.
To compile your design, click Start Compilation on the Processing menu in the Intel® Quartus® Prime software. You can use the generated .qip file to include relevant files into your project.
Programming an FPGA Device
After successfully compiling your design, program the targeted Intel FPGA device with the Intel® Quartus® Prime Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer to the Device Programming section in volume 3 of the Intel® Quartus® Prime Handbook.
Generated Files
The type of files generated in your project directory and their names may vary depending on the custom variation of the IP core you created.
File Name | Description |
---|---|
<variation_name>.v or
<variation_name>.vhd |
A IP core variation file, which defines a VHDL or Verilog HDL top-level description of the custom IP core. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the Intel® Quartus® Prime software. |
<variation_name>.bsf | Intel® Quartus® Prime symbol file for the IP core variation. You can use this file in the Intel® Quartus® Prime block diagram editor. |
<variation_name>.qip and
<variation_name>.sip |
Contains Intel® Quartus® Prime project information for your IP core variations. |
<variation_name>.cmp | A VHDL component declaration file for the IP core variation. Add the contents of this file to any VHDL architecture that instantiates the IP core. |
<variation_name>.spd | Simulation Package Descriptor file. Specifies the files required for simulation. |
Testbench Files (in <variation_name>_testbench folder) | |
README.txt | Read me file for the testbench design. |
generate_sim.qpf
and
generate_sim.qsf |
Dummy Intel® Quartus® Prime project and project setting file. Use this to start the Intel® Quartus® Prime in the correct directory to launch the generate_sim_verilog.tcl and generate_sim_vhdl.tcl files. |
generate_sim_verilog.tcl
and
generate_sim_vhdl.tcl |
A Tcl script to generate the DUT VHDL or Verilog HDL simulation model for use in the testbench. |
/testbench_vhdl/<variation_name>/
<variation_name>_tb.vhd
or
/testbench_verilog/<variation_name>/ <variation_name>_tb.v |
VHDL or Verilog HDL testbench that exercises your IP core variation in a third party simulator. |
/testbench_vhdl/<variation_name>/run_
<variation_name>_tb.tcl
or
/testbench_verilog/<variation_name>/run_ <variation_name>_tb.tcl |
A Tcl script for use with the ModelSim simulation software. |
/testbench_vhdl/<variation_name>/
<variation_name>_wave.do
or
/testbench_verilog/<variation_name>/ <variation_name>_wave.do |
A signal tracing macro script used with the ModelSim simulation software to display testbench signals. |
/testbench_vhdl/models
or
/testbench_verilog/models |
A directory containing VHDL and Verilog HDL models of the Ethernet generators and monitors used by the generated testbench. |
Design Constraint File No Longer Generated
For a new Triple-Speed Ethernet IP core created using the Intel® Quartus® Prime software version 13.0 or later, the software no longer generate the <variation_name>_constraints.tcl file that contains the necessary constraints for the compilation of your IP core variation.
The following table lists the recommended Quartus pin assignments that you can set in your design.
Pin Assignment | Assignment Value | Description | Design Pin |
---|---|---|---|
FAST_INPUT_REGISTER | ON | To optimize I/O timing for MII, GMII and TBI interface. | MII, GMII, RGMII, TBI input pins. |
FAST_OUTPUT_REGISTER | ON | To optimize I/O timing for MII, GMII and TBI interface. | MII, GMII, RGMII, TBI output pins. |
IO_STANDARD | 1.4-V PCML or 1.5-V PCML | I/O standard for GXB serial input and output pins. | GXB transceiver serial input and output pins. |
IO_STANDARD | LVDS | I/O standard for LVDS/IO serial input and output pins. | LVDS/IO transceiver serial input and output pins. |
GLOBAL_SIGNAL | Global clock | To assign clock signals to use the global clock network. Use this setting to guide the Intel® Quartus® Prime software in the fitter process for better timing closure. |
|
GLOBAL_SIGNAL | Regional clock | To assign clock signals to use the regional clock network. Use this setting to guide the Intel® Quartus® Prime software in the fitter process for better timing closure. |
|
GLOBAL_SIGNAL | OFF | To prevent a signal to be used as a global signal. | Signals
for
Arria® V devices:
|
Parameter Settings
This chapter describes the parameters and how they affect the behavior of the IP core. Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface.
Core Configuration
Name | Value | Description |
---|---|---|
Core Variation |
|
Determines the primary blocks to include in the variation. |
Enable ECC protection | On/Off | Turn on this option to enable ECC protection for internal memory blocks. |
Interface |
|
Determines the Ethernet-side
interface of the MAC block.
Note: The RGMII interface is not supported in
Intel®
Stratix® 10,
Intel®
Arria® 10, and
Intel®
Cyclone® 10 GX devices from
Intel®
Quartus® Prime software version 17.1 onwards.
|
Use clock enable for MAC | On/Off | Turn on this option to include clock enable signals for the MAC. This option is only applicable for 10/100/1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations. |
Use internal FIFO | On/Off | Turn on this option to include internal FIFO buffers in the core. You can only include internal FIFO buffers in single-port MACs. |
Number of ports | 1, 4, 8, 12, 16, 20, and 24 | Specifies the number of Ethernet
ports supported by the IP core. This parameter is enabled if the
parameter Use
internal FIFO is turned off. A multiport MAC does not
support internal FIFO buffers.
Note: For
Intel®
Quartus® Prime
software version 17.1 onwards, the number of ports supported for
Triple-Speed Ethernet
designs targeting
Intel®
Stratix® 10,
Intel®
Arria® 10, and
Intel®
Cyclone® 10 GX devices is 8. This is
applicable only when you select LVDS I/O for the Transceiver type option.
|
Transceiver type |
|
This option is only available for
variations that include the PCS block.
Note: There may be a performance risk if you use the
Triple-Speed Ethernet IP
variant with LVDS I/O for PMA implementation in
Intel®
Arria® 10 devices for
Intel®
Quartus® Prime software version 17.0.2 and
earlier. To avoid the performance risk,
Intel®
recommends that you regenerate the
Triple-Speed Ethernet IP
core and recompile the design in the
Intel®
Quartus® Prime software version 17.1 or later. To download
and install the software patch for
Intel®
Quartus® Prime version 17.0.2, refer to KDB link: Performance Risk Running Triple Speed Ethernet
LVDS in Arria 10 Devices.
|
Ethernet MAC Options
- Enable MAC 10/100 half duplex support (10/100 Small MAC variations)
- Align packet headers to 32-bit boundary (10/100 and 1000 Small MAC variations)
Name | Value | Description |
---|---|---|
Ethernet MAC Options | ||
Enable MAC 10/100 half duplex support | On/Off | Turn on this option to include support for half duplex operation on 10/100 Mbps connections. |
Enable local loopback on MII/GMII/RGMII | On/Off | Turn on this option to enable local loopback on the MAC’s MII, GMII, or RGMII interface. If you turn on this option, the loopback function can be dynamically enabled or disabled during system operation via the MAC configuration register. |
Enable supplemental MAC unicast addresses | On/Off | Turn on this option to include support for supplementary destination MAC unicast addresses for fast hardware-based received frame filtering. |
Include statistics counters | On/Off | Turn on this option
to include support for simple network monitoring protocol (SNMP) management
information base (MIB) and remote monitoring (RMON) statistics counter
registers for incoming and outgoing Ethernet packets.
By default, the width of all statistics counters are 32 bits. |
Enable 64-bit statistics byte counters | On/Off | Turn on this option to extend the width of selected statistics counters— aOctetsTransmittedOK, aOctetsReceivedOK, and etherStatsOctets—to 64 bits. |
Include multicast hashtable | On/Off | Turn on this option to implement a hash table, a fast hardware-based mechanism to detect and filter multicast destination MAC address in received Ethernet packets. |
Align packet headers to 32-bit boundary | On/Off | Turn on this option to include
logic that aligns all packet headers to a 32-bit boundary. This
helps reduce software overhead processing in realignment of data
buffers.
This option is available for MAC variations with 32 bits wide internal FIFO buffers and MAC variations without internal FIFO buffers. You must turn on this option if you intend to use the Triple-Speed Ethernet IP core with the Interniche TCP/IP protocol stack. |
Enable full-duplex flow control | On/Off | Turn on this option to include the logic for full-duplex flow control that includes pause frames generation and termination. |
Enable VLAN detection | On/Off | Turn on this option to include the logic for VLAN and stacked VLAN frame detection. When turned off, the MAC does not detect VLAN and staked VLAN frames. The MAC forwards these frames to the user application without processing them. |
Enable magic packet detection | On/Off | Turn on this option to include logic for magic packet detection (Wake-on LAN). |
MDIO Module | ||
Include MDIO module (MDC/MDIO) | On/Off | Turn on this option if you want to access external PHY devices connected to the MAC function. When turned off, the core does not include the logic or signals associated with the MDIO interface. |
Host clock divisor | — | Clock divisor to divide the MAC
control interface clock to produce the MDC clock output on the MDIO
interface. The default value is 40.
For example, if the MAC control interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be specified. Intel recommends that the division factor is defined such that the MDC frequency does not exceed 2.5 MHz. |
FIFO Options
Name | Value | Parameter |
---|---|---|
Width | ||
Width | 8 Bits and 32 Bits | Determines the data width in bits of the transmit and receive FIFO buffers. |
Depth | ||
Transmit | Between 64 and 64K | Determines the depth of the internal FIFO buffers. |
Receive |
Timestamp Options
Name | Value | Parameter |
---|---|---|
Timestamp | ||
Enable timestamping | On/Off | Turn on this parameter to enable time stamping on the transmitted and received frames. |
Enable PTP 1-step clock | On/Off | Turn on this parameter
to insert timestamp on PTP messages for 1-step clock based on the TX Timestamp
Insert Control interface.
This parameter is disabled if you do not turn on Enable timestamping. |
Timestamp fingerprint width | — | Use this parameter to set the width in bits for the timestamp fingerprint on the TX path. The default value is 4 bits. |
PCS/Transceiver Options
Name | Value | Parameter |
---|---|---|
PCS Options | ||
PHY ID (32 bit) | — | Configures the PHY ID of the PCS block. |
Enable SGMII bridge | On/Off | Turn on this option to add the
SGMII clock and rate-adaptation logic to the PCS block. This option
allows you to configure the PCS either in SGMII mode or 1000Base-X
mode. If your application only requires 1000BASE-X PCS, turning off
this option reduces resource usage.
In Cyclone® IV GX devices, REFCLK[0,1] and REFCLK[4,5] cannot connect directly to the GCLK network. If you enable the SGMII bridge, you must connect ref_clk to an alternative dedicated clock input pin. |
Transceiver Options—apply only to variations that include GXB transceiver blocks | ||
Export transceiver powerdown signal | On/Off | This option is not supported in
Stratix® V,
Arria® V,
Arria® V GZ,
and
Cyclone® V devices.
Turn on this option to export the powerdown signal of the GX transceiver to the top-level of your design. Powerdown is shared among the transceivers in a quad. Therefore, turning on this option in multiport Ethernet configurations maximizes efficient use of transceivers within the quad. Turn off this option to connect the powerdown signal internally to the PCS control register interface. This connection allows the host processor to control the transceiver powerdown in your system. |
Enable transceiver dynamic reconfiguration | On/Off | This option is always turned on in
devices other than
Arria®
GX and
Stratix®
II GX. When this
option is turned on, the
Intel® FPGA IP core includes the dynamic reconfiguration signals.
For designs targeting devices other than Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10, and Intel® Cyclone® 10 GX, Intel recommends that you instantiate the ALTGX_RECONFIG megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. For Arria® V, Cyclone® V, and Stratix® V designs, Intel recommends that you instantiate the Transceiver Reconfiguration Controller megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. The transceivers in the Arria® V, Cyclone® V, and Stratix® V designs are configured with Intel FPGA Custom PHY IP core. The Custom PHY IP core require two reconfiguration interfaces for external reconfiguration controller. For more information on the reconfiguration interfaces required, refer to the V-Series Transceiver PHY IP Core User Guide and the respective device handbook. For more information about quad sharing considerations, refer to Sharing PLLs in Devices with GIGE PHY. |
Starting channel number | 0 – 284 | Specifies the channel number for
the GXB transceiver block. In a multiport MAC, this parameter
specifies the channel number for the first port. Subsequent channel
numbers are in four increments.
In designs with multiple instances of GXB transceiver block (multiple instances of Triple-Speed Ethernet IP core with GXB transceiver block or a combination of Triple-Speed Ethernet IP core and other IP cores), Intel recommends that you set a unique starting channel number for each instance to eliminate conflicts when the GXB transceiver blocks share a transceiver quad. This option is not supported in Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices. For these devices, the channel numbers depends on the dynamic reconfiguration controller. |
Series V GXB Transceiver Options | ||
TX PLLs type |
|
This option is only available for
variations that include the PCS block for
Stratix® V and
Arria® V GZ
devices.
Specifies the TX phase-locked loops (PLLs) type—CMU or ATX—in the GXB transceiver for Series V devices. |
Enable SyncE Support | On/Off | Turn on this option to enable SyncE support by separating the TX PLL and RX PLL reference clock. |
TX PLL clock network |
|
This option is only available for
variations that include the PCS block for
Arria® V and
Cyclone® V
devices.
Specifies the TX PLL clock network type. |
Intel® Arria® 10 or Intel® Cyclone® 10 GX GXB Transceiver Options | ||
Enable Intel® Arria® 10 or Intel® Cyclone® 10 GX transceiver dynamic reconfiguration | On/Off | Turn on this option for the Intel® FPGA IP core to include the dynamic reconfiguration signals. |
Refer to the respective device handbook for more information on dynamic reconfiguration in Intel FPGA devices.
Functional Description
The Triple-Speed Ethernet IP core includes the following functions:
- 10/100/1000 Ethernet MAC
- 1000BASE-X/SGMII PCS With Optional Embedded PMA
- Intel FPGA IEEE 1588v2
10/100/1000 Ethernet MAC
- Variations with internal FIFO buffers—supports only single port.
- Variations without internal FIFO buffers—supports up to 24 ports (except for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices) and the ports can operate at different speeds.
- Small MAC—provides basic
functionalities of a MAC function using minimal resources.
Refer to 10/100/1000 Ethernet MAC Versus Small MAC for a feature comparison between the 10/100/1000 Ethernet MAC and small MAC.
The MAC function supports the following Ethernet frames: basic, VLAN and stacked VLAN, jumbo, and control frames.
MAC Architecture
The FIFO buffers, which you can configure to 8- or 32-bits wide, store the transmit and receive data. The buffer width determines the data width on the Avalon-ST receive and transmit interfaces. You can configure the FIFO buffers to operate in cut-through or store-and-forward mode using the rx_section_full and tx_section_full registers.
In a multiport MAC, the instances share the MDIO master and some configuration registers. You can use the Avalon-ST Multi-Channel Shared Memory FIFO core in Platform Designer to store the transmit and receive data.
Interfaces
- Avalon-ST on the system side.
- Avalon-ST sink port on transmit with
the following properties:
- Fixed data width, 8 bits, in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
- Packet support using start-of-packet (SOP) and end-of-packet (EOP) signals, and partial final packet signals.
- Error reporting.
- Variable-length ready latency specified by the tx_almost_full register.
- Avalon-ST source port on receive with
the following properties:
- Fixed data width of 8 bits in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
- Backpressure is supported only in MAC variations with internal FIFO buffers. Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds.
- Packet support using SOP and EOP signals, and partial final packet signals.
- Error reporting.
- Ready latency is zero in MAC variations without internal FIFO buffers. In MAC variations with internal FIFO buffers, the ready latency is two.
- Avalon-ST sink port on transmit with
the following properties:
- Media independent interfaces on the network side—select MII, GMII, or RGMII by setting the Interface option on the Core Configuration page or the ETH_SPEED bit in the command_config register.
- Control interface—an Avalon-MM slave port that provides access to 256 32-bit configuration and status registers, and statistics counters. This interface supports the use of waitrequest to stall the interconnect fabric for as many cycles as required.
- PHY management interface—implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers. This interface supports up to 32 PHY devices.
MAC variations without internal FIFO buffers implement the following additional interfaces:
- FIFO status interface—an Avalon-ST sink port that streams in the fill level of an external FIFO buffer. Only MAC variations without internal buffers implement this interface.
- Packet classification interface—an Avalon-ST source port that streams out receive packet classification information. Only MAC variations without internal buffers implement this interface.
Transmit Datapath
- In
MAC variations with internal FIFO buffers:
- Cut-through mode—transmission starts when the level of the FIFO level hits the transmit section-full threshold.
- Store and forward mode—transmission starts when a full packet is received.
- In MAC variations without internal FIFO buffers, transmission starts as soon as data is available on the Avalon-ST transmit interface.
IP Payload Re-alignment
Address Insertion
Frame Payload Padding
- 46 bytes for basic frames
- 42 bytes for VLAN tagged frames
- 38 bytes for stacked VLAN tagged frames
CRC-32 Generation
The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:
FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X 1 +1
The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus transmitted in the following order: X31, X30,..., X1, X0.
Interpacket Gap Insertion
In half-duplex mode, the MAC function constantly monitors the line. Transmission starts only when the line has been idle for a period of 96 bit times and any backoff time requirements have been satisfied. In accordance with the standard, the MAC function begins to measure the IPG when the m_rx_crs signal is deasserted.
Collision Detection in Half-Duplex Mode
When the MAC function detects collision during transmission, it stops the transmission and sends a 32-bit jam pattern instead. A jam pattern is a fixed pattern, 0x648532A6, and is not compared to the CRC of the frame. The probability of a jam pattern to be identical to the CRC is very low, 0.532%.
If the MAC function detects collision while transmitting the preamble or SFD field, it sends the jam pattern only after transmitting the SFD field, which subsequently results in a minimum of 96-bit fragment.
If the MAC function detects collision while transmitting the first 64 bytes, including the preamble and SFD fields, the MAC function waits for an interval equal to the backoff period and then retransmits the frame. The frame is stored in a 64-byte retransmit buffer. The backoff period is generated from a pseudo-random process, truncated binary exponential backoff.
The backoff time is a multiple of slot times. One slot is equal to a 512 bit times period. The number of the delay slot times, before the Nth retransmission attempt, is chosen as a uniformly distributed random integer in the following range:
0 ≤ r < 2k
k = min( n , N ), where n is the number of retransmissions and N = 10.
For example, after the first collision, the backoff period, in slot time, is 0 or 1. If a collision occurs during the first retransmission, the backoff period, in slot time, is 0, 1, 2, or 3.
The maximum backoff time, in 512 bit times slots, is limited by N set to 10 as specified in the IEEE Standard 802.3.
If collision occurs after 16 consecutive retransmissions, the MAC function reports an excessive collision condition by setting the EXCESS_COL bit in the command_config register to 1, and discards the current frame from the transmit FIFO buffer.
In networks that violate standard requirements, collision may occur after the transmission of the first 64 bytes. If this happens, the MAC function stops transmitting the current frame, discards the rest of the frame from the transmit FIFO buffer, and resumes transmitting the next available frame. You can check the LATE_COL register (command_config [12]) to verify if the MAC has discarded any frame due to collision.
Receive Datapath
Preamble Processing
The IEEE standard specifies that frames must be separated by an interpacket gap (IPG) of at least 96 bit times. The MAC function, however, can accept frames with an IPG of less than 96 bit times; at least 8-bytes and 6-bytes in RGMII/GMII (1000 Mbps operation) and RGMII/MII (10/100 Mbps operation) respectively.
The MAC function removes the preamble and SFD fields from valid frames.
Collision Detection in Half-Duplex Mode
Address Checking
- Unicast address—bit 0 of the destination address is 0.
- Multicast address—bit 0 of the destination address is 1.
- Broadcast address—all 48 bits of the destination address are 1.
The MAC function always accepts broadcast frames. If promiscuous mode is enabled (PROMIS_EN bit in the command_config register = 1), the MAC function omits address filtering and accepts all frames.
Unicast Address Checking
- The primary address, configured in the registers mac_0 and mac_1
- The supplementary addresses, configured in the following registers: smac_0_0/smac_0_1, smac_1_0/smac_1_1, smac_2_0/smac_2_1 and smac_3_0/smac_3_1
Otherwise, the MAC function discards the frame.
Multicast Address Resolution
The MAC function uses a 64-entry hash table in the register space, multicast hash table, to implement the hardware multicast address resolution engine as shown in figure below. The host processor must build the hash table according to the specified algorithm. A 6-bit code is generated from each multicast address by XORing the address bits as shown in table below. This code represents the address of an entry in the hash table. Write one to the most significant bit in the table entry. All multicast addresses that hash to the address of this entry are valid and accepted.
You can choose to generate the 6-bit code from all 48 bits of the destination address by setting the MHASH_SEL bit in the command_config register to 0, or from the lower 24 bits by setting the MHASH_SEL bit to 1. The latter option is provided if you want to omit the manufacturer's code, which typically resides in the upper 24 bits of the destination address, when generating the 6-bit code.
Hash Code Bit | Value |
---|---|
0 | xor multicast MAC address bits 7:0 |
1 | xor multicast MAC address bits 15:8 |
2 | xor multicast MAC address bits 23:16 |
3 | xor multicast MAC address bits 31:24 |
4 | xor multicast MAC address bits 39:32 |
5 | xor multicast MAC address bits 47:40 |
Hash Code Bit | Value |
---|---|
0 | xor multicast MAC address bits 3:0 |
1 | xor multicast MAC address bits 7:4 |
2 | xor multicast MAC address bits 11:8 |
3 | xor multicast MAC address bits 15:12 |
4 | xor multicast MAC address bits 19:16 |
5 | xor multicast MAC address bits 23:20 |
The MAC function checks each multicast address received against the hash table, which serves as a fast matching engine, and a match is returned within one clock cycle. If there is no match, the MAC function discards the frame.
All multicast frames are accepted if all entries in the hash table are one.
Frame Type Validation
- Length/type < 0x600—the field represents the payload length of a basic Ethernet frame. The MAC function continues to check the frame and payload lengths.
- Length/type >= 0x600—the field
represents the frame type.
- Length/type = 0x8100—VLAN or stacked
VLAN tagged frames. The MAC function continues to check the frame and payload
lengths, and asserts the following signals:
- for VLAN frames, rx_err_stat[16] in MAC variations with internal FIFO buffers or pkt_class_data[1] in MAC variations without internal FIFO buffers
- for stacked VLAN frames, rx_err_stat[17] in MAC variations with internal FIFO buffers or pkt_class_data[0] in MAC variations without internal FIFO buffers.
- Length/type = 0x8088—control frames.
The next two bytes, the Opcode field, indicate the type of control frame.
- For pause frames (Opcode = 0x0001), the MAC function continues to check the frame and payload lengths. For valid pause frames, the MAC function proceeds with pause frame processing. The MAC function forwards pause frames to the user application only when the PAUSE_FWD bit in the command_config register is set to 1.
- For other types of control frames, the MAC function accepts the frames and forwards them to the user application only when the CNTL_FRM_ENA bit in the command_config register is set to 1.
- Length/type = 0x8100—VLAN or stacked
VLAN tagged frames. The MAC function continues to check the frame and payload
lengths, and asserts the following signals:
- For other field values, the MAC function forwards the receive frame to the user application.
Payload Pad Removal
- 46 bytes for basic MAC frames
- 42 bytes for VLAN tagged frames
- 38 bytes for stacked VLAN tagged frames
When padding removal is turned off, complete frames including the padding are forwarded to the Avalon-ST receive interface.
CRC Checking
FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X 1 +1
The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus received in the following order: X31, X30,..., X1, X0.
If the MAC function detects CRC-32 error, it marks the frame invalid by asserting the following signals:
- rx_err[2] in MAC variations with internal FIFO buffers.
- data_rx_error[1] in MAC variations without internal FIFO buffers.
The MAC function discards frames with CRC-32 error if the RX_ERR_DISC bit in the command_config register is set to 1.
For frames less than the required minimum length, the MAC function forwards the CRC-32 field to the user application if the CRC_FWD and PAD_EN bits in the command_config register are 1 and 0 respectively. Otherwise, the CRC-32 field is removed from the frame.
Length Checking
The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the different frame types:
- Basic frames—the value specified in the frm_length register
- VLAN tagged frames—the value specified in the frm_length register plus four
- Stacked VLAN tagged frames—the value specified in the frm_length register plus eight
To prevent FIFO buffer overflow, the MAC function truncates the frame if it is more than 11 bytes longer than the allowed maximum length.
For frames of a valid length, the MAC function continues to check the payload length if the NO_LGTH_CHECK bit in the command_config register is set to 0. The MAC function keeps track of the payload length as it receives a frame, and checks the length against the length/type field in basic MAC frames or the client length/type field in VLAN tagged frames. The payload length is valid if it satisfies the following conditions:
- The actual payload length matches the value in the length/type or client length/type field.
- Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.
- VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.
- Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding 1536.
If the frame or payload length is not valid, the MAC function asserts one of the following signals to indicate length error:
- rx_err[1] in MACs with internal FIFO buffers.
- data_rx_error[0] in MACs without internal FIFO buffers.
Frame Writing
For MAC variations with internal FIFO buffers, the MAC function writes the frame to the internal receive FIFO buffers.For MAC variations without internal FIFO buffers, it forwards the frame to the Avalon-ST receive interface.
MAC variations without internal FIFO buffers do not support backpressure on the Avalon-ST receive interface. In this variation, if the receiving component is not ready to receive data from the MAC function, the frame gets truncated with error and subsequent frames are also dropped with error.
IP Payload Alignment
Bits | |||
---|---|---|---|
31...24 | 23...16 | 15...8 | 7...0 |
Byte 0 | Byte 1 | Byte 2 | Byte 3 |
Byte 4 | Byte 5 | Byte 6 | Byte 7 |
Bits | |||
---|---|---|---|
31...24 | 23...16 | 15...8 | 7...0 |
padded with zeros | Byte 0 | Byte 1 | |
Byte 2 | Byte 3 | Byte 4 | Byte 5 |
MAC Transmit and Receive Latencies
- Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon-ST interface.
- Receive latency is the number of clock cycles the MAC function takes to present the first bit on the Avalon-ST interface after the bit was received on the network-side interface (MII/GMII/RGMII).
MAC Configuration | Latency (Clock Cycles) 2 3 | |
---|---|---|
Transmit | Receive | |
MAC with Internal FIFO Buffers 4 | ||
GMII in cut-through mode | 32 | 110 |
MII in cut-through mode | 41 | 218 |
RGMII in gigabit and cut-through mode | 33 | 113 |
RGMII in 10/100 Mbps and cut-through mode | 42 | 221 |
MAC without Internal FIFO Buffers 5 | ||
GMII | 11 | 37 |
MII | 22 | 77 |
RGMII in gigabit mode | 12 | 40 |
RGMII in10/100 Mbps | 23 | 80 |
FIFO Buffer Thresholds
- Almost empty
- Almost full
- Section empty
- Section full
These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers. The FIFO buffer thresholds are configured via the registers.
Receive Thresholds
Threshold | Register Name | Description |
---|---|---|
Almost empty | rx_almost_empty | The number of unread
entries in the FIFO buffer before the buffer is empty. When the level of the
FIFO buffer reaches this threshold, the MAC function asserts the
ff_rx_a_empty signal.
The MAC function stops reading from the FIFO buffer and subsequently stops
transferring data to the user application to avoid buffer underflow.
When the MAC function detects an EOP, it transfers all data to the user application even if the number of unread entries is below this threshold. |
Almost full | rx_almost_full | The number of unwritten
entries in the FIFO buffer before the buffer is full. When the level of the
FIFO buffer reaches this threshold, the MAC function asserts the
ff_rx_a_full signal. If
the user application is not ready to receive data (ff_rx_rdy = 0), the MAC function performs
the following operations:
If the RX_ERR_DISC bit in the command_config register is set to 1 and the section-full (rx_section_full) threshold is set to 0, the MAC function discards frames with error received on the Avalon-ST interface. |
Section empty | rx_section_empty | An early indication
that the FIFO buffer is getting full. When the level of the FIFO buffer hits
this threshold, the MAC function generates an XOFF pause frame to indicate FIFO
congestion to the remote Ethernet device. When the FIFO level goes below this
threshold, the MAC function generates an XON pause frame to indicate its
readiness to receive new frames.
To avoid data loss, you can use this threshold as an early warning to the remote Ethernet device on the potential FIFO buffer congestion before the buffer level hits the almost-full threshold. The MAC function truncates receive frames when the buffer level hits the almost-full threshold. |
Section full | rx_section_full | The section-full
threshold indicates that there are sufficient entries in the FIFO buffer for
the user application to start reading from it. The MAC function asserts the
ff_rx_dsav signal when
the buffer level hits this threshold.
Set this threshold to 0 to enable store and forward on the receive datapath. In the store and forward mode, the ff_rx_dsav signal remains deasserted. The MAC function asserts the ff_rx_dval signal as soon as a complete frame is written to the FIFO buffer. |
Transmit Thresholds
Threshold | Register Name | Description |
---|---|---|
Almost empty | tx_almost_empty | The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_tx_a_empty signal. The MAC function stops reading from the FIFO buffer and sends the Ethernet frame with GMII / MII/ RGMII error to avoid FIFO underflow. |
Almost full | tx_almost_full | The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_tx_a_full signal. The MAC function deasserts the ff_tx_rdy signal to backpressure the Avalon-ST transmit interface. |
Section empty | tx_section_empty | An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer reaches this threshold, the MAC function deasserts the ff_tx_septy signal. This threshold can serve as a warning about potential FIFO buffer congestion. |
Section full | tx_section_full | This threshold
indicates that there are sufficient entries in the FIFO buffer to start frame
transmission.
Set this threshold to 0 to enable store and forward on the transmit path. When you enable the store and forward mode, the MAC function forwards each frame as soon as it is completely written to the transmit FIFO buffer. |
Transmit FIFO Buffer Underflow
- The MAC function asserts the RGMII/GMII/MII error signals (tx_control/gm_tx_err/m_tx_err) to indicate that the fragment transferred is not valid.
- The MAC function deasserts the RGMII/GMII/MII transmit enable signals (tx_control/gm_tx_en/m_tx_en) to terminate the frame transmission.
- After the underflow, the user application completes the frame transmission.
- The transmitter control discards any new data in the FIFO buffer until the end of frame is reached.
- The MAC function starts to transfer data on the RGMII/GMII/MII when the user application sends a new frame with an SOP.
Congestion and Flow Control
- Remote device congestion—the receiving device experiences congestion and requests the MAC function to stop sending data.
- Receive FIFO buffer congestion—when the receive FIFO buffer is almost full, the MAC function sends a pause frame to the remote device requesting the remote device to stop sending data.
- Local device congestion—any device connected to the MAC function, such as a processor, can request the remote device to stop data transmission.
Remote Device Congestion
You can configure the MAC function to ignore pause frames by setting the PAUSE_IGNORE bit in the command_config register is set to 1.
Receive FIFO Buffer and Local Device Congestion
For MAC variations with internal FIFO buffers, the MAC function generates an XOFF pause frame when the level of the FIFO buffer reaches the section-empty threshold (rx_section_empty). If transmission is in progress, the MAC function waits for the transmission to complete before generating the pause frame. The fill level of an external FIFO buffer is obtained via the Avalon-ST receive FIFO status interface.
When generating a pause frame, the MAC function fills the pause quanta bytes P1 and P2 with the value configured in the pause_quant register. The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers, and the destination address is set to a fixed multicast address, 01-80-C2-00-00-01 (0x010000c28001).
The MAC function automatically generates an XON pause frame when the FIFO buffer section-empty flag is deasserted and the current frame transmission is completed. The user application can trigger the generation of an XON pause frame by clearing the XOFF_GEN bit and signal, and subsequently setting the XON_GEN bit to 1 or asserting the XON_GEN signal.
When generating an XON pause frame, the MAC function fills the pause quanta (payload bytes P1 and P2) with 0x0000 (zero quanta). The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers and the destination address is set to a fixed multicast address, 01-80-C2-00-00-01 (0x010000c28001).
In addition to the flow control mechanism, the MAC function prevents an overflow by truncating excess frames. The status bit, rx_err[3], is set to 1 to indicate such errors. The user application should subsequently discard these frames by setting the RX_ERR_DISC bit in the command_config register to 1.
Magic Packets
The defined sequence is a stream of six consecutive 0xFF bytes followed by a sequence of 16 consecutive unicast MAC addresses. The unicast address is the address of the node to be awakened.
The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header, optional padding and CRC.
Sleep Mode
Intel recommends that you do not put a node to sleep if you disable magic packet detection.
Network transmission is disabled when a node is put to sleep. The receiver remains enabled, but it ignores all traffic from the line except magic packets to allow a remote agent to wake up the node. In the sleep mode, only etherStatsPkts and etherStatsOctets count the traffic statistics.
Magic Packet Detection
- Any multicast address
- A broadcast address
- The primary MAC address configured in the mac_0 and mac_1 registers
- Any of the supplementary MAC addresses configured in the following registers if they are enabled: smac_0_0, smac_0_1, smac_1_0, smac_1_1, smac_2_0, smac_2_1, smac_3_0 and smac_3_1
When the MAC function detects a magic packet, the WAKEUP bit in the command_config register is set to 1, and the etherStatsPkts and etherStatsOctets statistics registers are incremented.
Magic packet detection is disabled when the SLEEP bit in the command_config register is set to 0. Setting the SLEEP bit to 0 also resets the WAKEUP bit to 0 and resumes the transmit and receive operations.
Local Loopback
To enable local loopback:
-
Initiate software reset by setting the
SW_RESET bit in
command_config register to
1.
Software reset disables the transmit and receive operations, flushes the internal FIFOs, and clears the statistics counters. The SW_RESET bit is automatically cleared upon completion.
- When software reset is complete, enable local loopback on the MAC's MII/GMII/RGMII by setting the LOOP_ENA bit in command_config register to 1.
- Enable transmit and receive operations by setting the TX_ENA and RX_ENA bits in command_config register to 1.
- Initiate frame transmission.
- Compare the statistics counters aFramesTransmittedOK and aFramesReceivedOK to verify that the transmit and receive frame counts are equal.
- Check the statistics counters ifInErrors and ifOutErrors to determine the number of packets transmitted and received with errors.
- To disable loopback, initiate a software reset and set the LOOP_ENA bit in command_config register to 0.
MAC Error Correction Code (ECC)
Core Variation | ECC Protection Support |
---|---|
10/100/1000 Mb Ethernet MAC | Protects the following
options:
transmit and receive FIFO buffer Retransmit buffer (if half duplex is enabled) Statistic counters (if enabled) Multicast hashtable (if enabled) |
10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS | Protects the following
options:
transmit and receive FIFO buffer Retransmit buffer (if half duplex is enabled) Statistic counters (if enabled) Multicast hashtable (if enabled) SGMII bridge (if enabled) |
1000BASE-X/SGMII PCS only | Protects the SGMII bridge (if enabled) |
1000 Mb Small MAC | Protects the transmit and receive FIFO buffer |
10/100 Mb Small MAC | Protects the following
options:
transmit and receive FIFO buffer Retransmit buffer (if half duplex is enabled) |
When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and 1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the IP core.
- Single channel core configuration—eccstatus[1:0] output ports.
- Multi-channel core configuration—eccstatus_<n>[1:0] output ports, where eccstatus_0[1:0] is for channel 0, eccstatus_1[1:0] for channel 1, and so on.
MAC Reset
When you trigger a software reset, the MAC function sets the TX_ENA and RX_ENA bits in the command_config register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only disabled when the current frame transmission and reception complete.
- To trigger a hardware reset, assert the reset signal.
- To trigger a software reset, set the SW_RESET bit in the command_config register to 1. The SW_RESET bit is cleared automatically when the software reset ends.
Intel recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating speed or mode without changing other configurations, preserve the command_config register before performing the software reset and restore the register after the changing the MAC operating speed or mode.
PHY Management (MDIO)
To access each PHY device, write the PHY address to the MDIO register (mdio_addr0/1) followed by the transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the MDIO registers via the Avalon-MM interface.
For more information about the registers of a PHY device, refer to the specification provided with the device.
For more information about the MDIO registers, refer to MAC Configuration Register Space.
MDIO Connection
MDIO Frame Format
Type | PRE | Command | ||||||
---|---|---|---|---|---|---|---|---|
ST
MSB LSB |
OP
MSB LSB |
Addr1
MSB LSB |
Addr2
MSB LSB |
TA |
Data
MSB LSB |
Idle | ||
Read | 1 ... 1 | 01 | 10 | xxxxx | xxxxx | Z0 | xxxxxxxxxxxxxxxx | Z |
Write | 1 ... 1 | 01 | 01 | xxxxx | xxxxx | 10 | xxxxxxxxxxxxxxxx | Z |
Name | Description |
---|---|
PRE | Preamble. 32 bits of logical 1 sent prior to every transaction. |
ST | Start indication. Standard MDIO (Clause 22): 0b01. |
OP | Opcode. Defines the transaction type. |
Addr1 | The PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, the Addr1 field is set to the value configured in the mdio_addr0 register. For PHY device 1, the Addr1 field is set to the value configured in the mdio_addr1 register. |
Addr2 | Register Address. Each PHY can have up to 32 registers. |
TA | Turnaround time. Two bit times are reserved for read operations to switch the data bus from write to read for read operations. The PHY device presents its register contents in the data phase and drives the bus from the 2nd bit of the turnaround phase. |
Data | 16-bit data written to or read from the PHY device. |
Idle | Between frames, the MDIO data signal is tri-stated. |
Connecting MAC to External PHYs
- Gigabit Ethernet operation
- Programmable 10/100 Ethernet operation
- Programmable 10/100/1000 Ethernet operation
Gigabit Ethernet
A technology specific clock driver is required to generate a clock centered with the GMII or RGMII data from the MAC. The clock driver can be a PLL, a delay line or a DDR flip-flop.
Programmable 10/100/1000 Ethernet Operation
Programmable 10/100 Ethernet
On the receive path, connect the clock provided by the PHY device (2.5 MHz, 25 MHz or 125 MHz) to the MAC clock, rx_clk. The PHY interface is connected to both the MII (active PHY signals) and GMII of the MAC function.
On the transmit path, standard programmable PHY devices operating in 10/100 mode generate a 2.5 MHz (10 Mbps) or a 25 MHz (100 Mbps) clock. In gigabit mode, the PHY device expects a 125-MHz clock from the MAC function. Because the MAC function does not generate a clock output, an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices. In 10/100 mode, the clock generated by the MAC to the PHY can be tri-stated.
During transmission, the MAC control signal eth_mode selects either MII or GMII. The MAC function asserts the eth_mode signal when the MAC function operates in gigabit mode, which subsequently drives the MAC GMII to the PHY interface. The eth_mode signal is deasserted when the MAC function operates in 10/100 mode. In this mode, the MAC MII is driven to the PHY interface.
1000BASE-X/SGMII PCS With Optional Embedded PMA
You can configure the PCS function to include an embedded physical medium attachment (PMA) with a a serial transceiver or LVDS I/O and soft CDR. The PMA interoperates with an external physical medium dependent (PMD) device, which drives the external copper or fiber network. The interconnect between Intel FPGA and PMD devices can be TBI or 1.25 Gbps serial.
The PCS function supports the following external PHYs:
- 1000 BASE-X PHYs as is.
- 10BASE-T, 100BASE-T and 1000BASE-T PHYs if the PHYs support SGMII.
1000BASE-X/SGMII PCS Architecture
Transmit Operation
Frame Encapsulation
If the PCS function receives a frame from the MAC function with an error (gm_tx_err asserted during frame transmission), the PCS function encodes the error by inserting a /V/ character.
8b/10b Encoding
Receive Operation
Comma Detection
The comma detection function restarts the search for a valid comma character if the receive synchronization state machine loses the link synchronization.
8b/10b Decoding
Frame De-encapsulation
A /V/ character is decoded and sent to the MAC function as frame error. The state machine decodes sequences other than /I/ /I/ (Idle) or /I/ /S/ (Start of Frame) as wrong carrier.
During frame reception, the de-encapsulation state machine checks for invalid characters. When the state machine detects invalid characters, it indicates an error to the MAC function.
Synchronization
When link synchronization is acquired, the link synchronization state machine counts the number of invalid characters received. The state machine increments an internal error counter for each invalid character received and incorrectly positioned comma character. The internal error counter is decremented when four consecutive valid characters are received. When the counter reaches 4, the link synchronization is lost.
The PCS function drives the led_link signal to 1 when link synchronization is acquired. This signal can be used as a common visual activity check using a board LED.
The PCS function drives the led_panel_link signal to 1 when link synchronization is acquired for the PCS operating in 1000 Base-X without auto negotiation and SGMII mode without auto negotiation.
Carrier Sense
The carrier sense state machine drives the mii_rx_crs and led_crs signals to 1 when it detects an activity. The led_crs signal can be used as a common visual activity check using a board LED.
Collision Detection
When a collision happens, the collision detection state machine drives the mii_rx_col and led_col signals to 1. You can use the led_col signal as a visual check using a board LED.
Transmit and Receive Latencies
- Transmit latency is the time the PCS function takes to transmit the first bit on the PMA-PCS interface after the bit was first available on the MAC side interface (MII/GMII).
- Receive latency is the time the PCS function takes to present the first bit on the MAC side interface (MII/GMII) after the bit was received on the PMA-PCS interface.
PCS Configuration | Latency (ns) | |
---|---|---|
Transmit | Receive | |
Stratix® IV | ||
10-Mbps SGMII PCS with GXB | 3456 | 1454.85 |
100-Mbps SGMII PCS with GXB | 376 | 214.8 |
1000-Mbps SGMII PCS with GXB | 104 | 142.8 |
1000BASE-X with GXB | 8 | 48 |
10-Mbps SGMII PCS with LVDS I/O | 3064 | 1720 |
100-Mbps SGMII PCS with LVDS I/O | 384 | 280 |
1000-Mbps SGMII PCS with LVDS I/O | 136 | 192 |
1000BASE-X PCS with LVDS I/O | 40 | 96 |
Intel® Arria® 10 | ||
10-Mbps SGMII PCS with GXB | 3600 | 1867.65 |
100-Mbps SGMII PCS with GXB | 360 | 187.65 |
1000-Mbps SGMII PCS with GXB | 104 | 139.65 |
1000BASE-X with GXB | 8 | 48 |
10-Mbps SGMII PCS with LVDS I/O | 3208 | 1176 |
100-Mbps SGMII PCS with LVDS I/O | 368 | 256 |
1000-Mbps SGMII PCS with LVDS I/O | 136 | 192 |
1000BASE-X PCS with LVDS I/O | 40 | 96 |
Intel® Cyclone® 10 GX | ||
10-Mbps SGMII PCS with GXB | 3600 | 1867.65 |
100-Mbps SGMII PCS with GXB | 360 | 187.65 |
1000-Mbps SGMII PCS with GXB | 104 | 139.65 |
1000BASE-X with GXB | 8 | 48 |
10-Mbps SGMII PCS with LVDS I/O | 3208 | 1176 |
100-Mbps SGMII PCS with LVDS I/O | 368 | 256 |
1000-Mbps SGMII PCS with LVDS I/O | 136 | 192 |
1000BASE-X PCS with LVDS I/O | 40 | 96 |
Intel® Stratix® 10 | ||
10-Mbps SGMII PCS with LVDS I/O | 3336 | 1840 |
100-Mbps SGMII PCS with LVDS I/O | 456 | 280 |
1000-Mbps SGMII PCS with LVDS I/O | 112 | 208 |
1000BASE-X PCS with LVDS I/O with no Enable SGMII | 40 | 104 |
SGMII Converter
In 1000BASE-X mode, the PCS function always operates in gigabit mode and data duplication is disabled.
Transmit
In 100-Mbps mode, the transmit converter replicates each byte received by the PCS function 10 times. In 10 Mbps, the transmit converter replicates each byte transmitted from the MAC function to the PCS function 100 times.
Receive
In 100-Mbps mode, the receive converter transmits one byte out of 10 bytes received from the PCS function to the MAC function. In 10-Mbps, the receive converter transmits one byte out of 100 bytes received from the PCS function to the MAC function.
Auto-Negotiation
If the SGMII_ENA bit in the if_mode register is set to 0, the PCS function operates in 1000BASE-X. Otherwise, the operating mode is SGMII. The following sections describe the auto-negotiation process for each operating mode.
When simulating your design, you can disable auto-negotiation to reduce the simulation time. If you enable auto-negotiation in your design, set the link_timer time to a smaller value to reduce the auto-negotiation link timer in the simulation.
1000BASE-X Auto-Negotiation
When the link_timer time expires, the PCS dev_ability register is advertised, with the ACK bit set to 0 for the link partner. The auto-negotiation state machine checks for three consecutive /C/ sequences received from the link partner.
The auto-negotiation state machine then sets the ACK bit to 1 in the advertised dev_ability register and checks if three consecutive /C/ sequences are received from the link partner with the ACK bit set to 1.
Auto-negotiation waits for the value configured in the link_timer register to ensure no more consecutive /C/sequences are received from the link partner. The auto-negotiation is successfully completed when three consecutive idle sequences are received after the link timer expires.
After auto-negotiation completes successfully, the user software reads both the dev_ability and partner_ability register and proceed to resolve priority for duplex mode and pause mode. If the design contains a MAC and PCS, the user software configures the MAC with a proper resolved pause mode by setting the PAUSE_IGNORE bit in command_config register. To disable pause frame generation based on the receive FIFO buffer level, you should set the rx_section_empty register accordingly.
Once auto-negotiation completes successfully, the ability advertised by the link partner device is available in the partner_ability register and the AUTO_NEGOTIATION_COMPLETE bit in the status register is set to 1.
The PCS function restarts auto-negotiation when link synchronization is lost and reacquired, or when you set the RESTART_AUTO_NEGOTIATION bit in the PCS control register to 1.
SGMII Auto-Negotiation
Possible application of SGMII auto-negotiation in MAC mode and PHY mode.
If the SGMII_ENA and USE_SGMII_AN bits in the if_mode register are 1, the PCS function is automatically configured with the capabilities advertised by the PHY device once the auto-negotiation completes.
If the SGMII_ENA bit is 1 and the USE_SGMII_AN bit is 0, the PCS function can be configured with the SGMII_SPEED and SGMII_DUPLEX bits in the if_mode register.
If the SGMII_ENA bit is 1 and the SGMII_AN_MODE bit is 1 (SGMII PHY Mode auto-negotiation is enabled) the speed and duplex mode resolution will be resolved based on the value that you set in the dev_ability register once auto negotiation is done. You should use set to the PHY mode if you want to advertise the link speed and duplex mode to the link partner.
For more information, refer to CISCO Serial-GMII Specifications.
PHY Loopback
On transmit, the SERDES must serialize tbi_tx_d[0], the least significant bit of the TBI output bus first and tbi_tx_d[9], the most significant bit of the TBI output bus last to ensure the remote node receives the data correctly, as figure below illustrates.
On receive, the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last, as figure below illustrates.
PHY Loopback
The serial loopback option is not supported in Cyclone® IV devices with GX transceiver.
PHY Power-Down
When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmit and the TBI receive interfaces are ignored. The management interface remains active and responds to management transactions from the MAC layer device.
Power-Down in PCS Variations with Embedded PMA
For designs targeting devices other than Stratix V, you can export the power-down signals to implement your own power-down logic to efficiently use the transceivers within a particular transceiver quad. Turn on the Export transceiver powerdown signal parameter to export the signals.
Reset
In PCS variations with embedded PMA, assert the respective reset signals or the power-down signal to trigger a hardware reset. You must assert the reset signal subsequent to asserting the reset_rx_clk, reset_tx_clk, or gbx_pwrdn_in signal. The reset sequence is also initiated when the active-low rx_freqlocked signal goes low.
For more information about the rx_freqlocked signal and transceiver reset, refer to the transceiver handbook of the respective device family.
Assert the reset or gxb_pwrdn_in signals to perform a hardware reset on MAC with PCS and embedded PMA variation.
Intel FPGA IEEE 1588v2 Feature
This feature is supported in Arria® V, Intel® Arria® 10, Cyclone® V, Intel® Cyclone® 10 GX, Intel® MAX® 10, Stratix® V, and Intel® Stratix® 10 device families.
IEEE 1588v2 Supported Configurations
- 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded serial PMA without FIFO buffer in full-duplex mode
- 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded LVDS I/O without FIFO buffer in full-duplex mode
- 10/100/1000-Mbps MAC without FIFO buffer in full-duplex mode
IEEE 1588v2 Features
- Supports 4 types of PTP clock on the
transmit datapath:
- Master and slave ordinary clock
- Master and slave boundary clock
- End-to-end (E2E) transparent clock
- Peer-to-peer (P2P) transparent clock
- Supports PTP message types:
- PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
- PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce, Management, and Signaling.
- Supports simultaneous 1-step and
2-step clock synchronizations on the transmit datapath.
- 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message or updates the correction field with residence time.
- 2-step clock synchronization—The MAC function provides accurate timestamp and the related fingerprint for all PTP message.
- Supports the following PHY operating
speed accuracy:
- random error:
- 10Mbps—NA
- 100Mbps—timestamp accuracy of ± 5 ns
- 1000Mbps—timestamp accuracy of ± 2 ns
- static error—timestamp accuracy of ± 3 ns
- random error:
- Supports IEEE 802.3, UDP/IPv4, and UDP/IPv6 transfer protocols for the PTP frames.
- Supports untagged, VLAN tagged, Stacked VLAN Tagged PTP frames, and any number of MPLS labels.
- Supports configurable register for timestamp correction on both transmit and receive datapaths.
- Supports Time-of-Day (ToD) clock that provides a stream of 64-bit and 96-bit timestamps.
Architecture
Transmit Datapath
- For 1-step clock synchronization:
- Timestamp insertion depends on the PTP device and message type.
- The MAC function inserts a timestamp in the Sync PTP message if the PTP clock operates as ordinary or boundary clock.
- Depending on the PTP device and message type, the MAC function updates the residence time in the correction field of the PTP frame when the client asserts tx_etstamp_ins_ctrl_residence_time_update. The residence time is the difference between the egress and ingress timestamps.
- For PTP frames encapsulated using the UDP/IPv6 protocol, the MAC function performs UDP checksum correction using extended bytes in the PTP frame.
- The MAC function re-computes and re-inserts CRC-32 into the PTP frames after each timestamp or correction field insertion.
- For 2-step clock synchronization, the MAC function returns the timestamp and the associated fingerprint for all transmit frames when the client asserts tx_egress_timestamp_request_valid.
PTP Message | Ordinary Clock | Boundary Clock | E2E Transparent Clock | P2P Transparent Clock | ||||
---|---|---|---|---|---|---|---|---|
Insert Time stamp | Insert Correction | Insert Time stamp | Insert Correction | Insert Time stamp | Insert Correction | Insert Time stamp | Insert Correction | |
Sync | Yes (1) | No | Yes (1) | No | No | Yes (2) | No | Yes (2) |
Delay_Req | No | No | No | No | No | Yes (2) | No | Yes (2) |
Pdelay_Req | No | No | No | No | No | Yes (2) | No | No |
Pdelay_Resp | No | Yes (1), (2) | No | Yes (1), (2) | No | Yes (2) | No | Yes (1), (2) |
Delay_Resp | No | No | No | No | No | No | No | No |
Follow_Up | No | No | No | No | No | No | No | No |
Pdelay_Resp_Follow_Up | No | No | No | No | No | No | No | No |
Announce | No | No | No | No | No | No | No | No |
Signaling | No | No | No | No | No | No | No | No |
Management | No | No | No | No | No | No | No | No |
Notes to Table 1 :
|
Receive Datapath
Frame Format
- IEEE 802.3
- UDP/IPv4
- UDP/IPv6
PTP Frame in IEEE 802.3
Note to Figure 1 :
- For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.
PTP Frame over UDP/IPv4
Note to Figure 1 :
- For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.
PTP Frame over UDP/IPv6
Note to Figure 1 :
- For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.
Configuration Register Space
MAC Configuration Register Space
In multiport MACs, a contiguous register space is allocated for all ports and accessed via the Avalon-MM control interface. For example, if the register space base address for the first port is 0x00, the base address for the next port is 0x100 and so forth. The registers that are shared among the instances occupy the register space of the first port. Updating these registers in the register space of other ports has no effect on the configuration.
Dword Offset | Section | Description |
---|---|---|
0x00 – 0x17 | Base Configuration | Base registers to
configure the MAC function. At the minimum, you must configure the following
functions:
The following registers are shared among all instances of a multiport MAC:
For more information about the base configuration registers, refer to Base Configuration Registers (Dword Offset 0x00 – 0x17). |
0x18 – 0x38 | Statistics Counters | Counters collecting traffic statistics. For more information about the statistics counters, refer to Statistics Counters (Dword Offset 0x18 – 0x38). |
0x3A | Transmit Command | Transmit and receive datapaths control register. For more information about these registers, see Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B). |
0x3B | Receive Command | |
0x3C – 0x3E | Extended Statistics Counters | Upper 32 bits of selected statistics counters. These registers are used if you turn on the option to use extended statistics counters. For more information about these counters, refer to Statistics Counters (Dword Offset 0x18 – 0x38) . |
0x3F | Reserved | Unused. |
0x40 – 0x7F | Multicast Hash Table | 64-entry write-only
hash table to resolve multicast addresses. Only bit 0 in each entry is
significant. When you write a 1 to a dword offset in the hash table, the MAC
accepts all multicast MAC addresses that hash to the value of the address (bits
5:0). Otherwise, the MAC rejects the multicast address. This table is cleared
during reset.
Hashing is not supported in 10/100 and 1000 Mbps Small MAC core variations. |
0x80 – 0x9F | MDIO Space 0
or PCS Function Configuration |
MDIO
Space 0 and MDIO Space 1 map to registers 0 to 31 of the PHY devices whose
addresses are configured in the
mdio_addr0 and
mdio_addr1 registers
respectively. For example, register 0 of PHY device 0 maps to dword offset
0x80, register 1 maps to dword offset 0x81 and so forth.
Reading or writing to MDIO Space 0 or MDIO Space 1 immediately triggers a corresponding MDIO transaction to read or write the PHY register. Only bits [15:0] of each register are significant. Write 0 to bits [31:16] and ignore them on reads. If your variation does not include the PCS function, you can use MDIO Space 0 and MDIO Space 1 to map to two PHY devices. If your MAC variation includes the PCS function, the PCS function is always device 0 and its configuration registers (PCS Configuration Register Space) occupy MDIO Space 0. You can use MDIO Space 1 to map to a PHY device. |
0xA0 – 0xBF | MDIO Space 1 | |
0xC0 – 0xC7 | Supplementary Address | Supplementary unicast addresses. For more information about these addresses, refer to Supplementary Address (Dword Offset 0xC0 – 0xC7). |
0xC8 – 0xCF | Reserved (1) | Unused. |
0xD0 – 0xD6 | IEEE 1588v2 Feature | Registers to configure the IEEE 1588v2 feature. For more information about these registers, refer to IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6). |
0xD7 – 0xFF | Reserved (1) | Unused. |
Note to Table 1:
|
Base Configuration Registers (Dword Offset 0x00 – 0x17)
The following table lists the base registers you can use to configure the MAC function. A software reset does not reset these registers except the first two bits (TX_ENA and RX_ENA = 0) in the command_config register.
Dword
Offset |
Name | R/W | Description | HW Reset |
---|---|---|---|---|
0x00 | rev | RO |
|
<IP version number> |
0x01 | scratch (1) | RW | Scratch register. Provides a memory location for you to test the device memory operation. | 0 |
0x02 | command_config | RW | MAC configuration register. Use
this register to control and configure the MAC function. The MAC
function starts operation as soon as the transmit and receive enable
bits in this register are turned on.
Intel,
therefore, recommends that you configure this register last.
See Command_Config Register (Dword Offset 0x02) for the bit description. |
0 |
0x03 | mac_0 | RW | 6-byte
MAC primary address. The first four most significant bytes of the MAC address
occupy
mac_0 in reverse
order. The last two bytes of the MAC address occupy the two least significant
bytes of
mac_1 in reverse
order.
For example, if the MAC address is 00-1C-23-17-4A-CB, the following assignments are made: mac_0 = 0x17231c00 mac_1 = 0x0000CB4a Ensure that you configure these registers with a valid MAC address if you disable the promiscuous mode (PROMIS_EN bit in command_config = 0). |
0 |
0x04 | mac_1 | RW | 0 | |
0x05 | frm_length | RW/
RO |
|
1518 |
0x06 | pause_quant | RW |
|
0 |
0x07 | rx_section_empty | RW/
RO |
Variable-length
section-empty threshold of the receive FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold. This threshold is typically set to (FIFO
Depth – 16).
Set this threshold to a value that is below the rx_almost_full threshold and above the rx_section_full or rx_almost_empty threshold. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16). |
0 |
0x08 | rx_section_full | RW/
RO |
Variable-length
section-full threshold of the receive FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold.
For cut-through mode, this threshold is typically set to 16. Set this threshold to a value that is above the rx_almost_empty threshold. For store-and-forward mode, set this threshold to 0. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 16. |
0 |
0x09 | tx_section_empty | RW/
RO |
Variable-length
section-empty threshold of the transmit FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold. This threshold is typically set to (FIFO
Depth – 16).
Set this threshold to a value below the rx_almost_full threshold and above the rx_section_full or rx_almost_empty threshold. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16). |
0 |
0x0A | tx_section_full | RW/
RO |
Variable-length
section-full threshold of the transmit FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold.
For cut-through mode, this threshold is typically set to 16. Set this threshold to a value above the tx_almost_empty threshold. For store-and-forward mode, set this threshold to 0. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 16. |
0 |
0x0B | rx_almost_empty | RW/
RO |
Variable-length
almost-empty threshold of the receive FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold.
Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8. |
0 |
0x0C | rx_almost_full | RW/
RO |
Variable-length
almost-full threshold of the receive FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold.
Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8. |
0 |
0x0D | tx_almost_empty | RW/
RO |
Variable-length
almost-empty threshold of the transmit FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold.
Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8. |
0 |
0x0E | tx_almost_full | RW/
RO |
Variable-length
almost-full threshold of the transmit FIFO buffer. Use the depth of your FIFO
buffer to determine this threshold.
You must set this register to a value greater than or equal to 3. A value of 3 indicates 0 ready latency; a value of 4 indicates 1 ready latency, and so forth. Because the maximum ready latency on the Avalon-ST interface is 8, you can only set this register to a maximum value of 11. This threshold is typically set to 3. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 3. |
0 |
0x0F | mdio_addr0 | RW |
|
0 |
0x10 | mdio_addr1 | RW | 1 | |
0x11 | holdoff_quant | RW |
|
0xFFFF |
0x12 – 0x16 | Reserved | — | — | 0 |
0x17 | tx_ipg_length | RW |
|
0 |
Note to Table 1 :
|
Command_Config Register (Dword Offset 0x02)
At the minimum, you must configure the TX_ENA and RX_ENA bits to 1 to start the MAC operations. When configuring the command_config register, Intel® recommends that you configure the TX_ENA and RX_ENA bits the last because the MAC function immediately starts its operations once these bits are set to 1.
Bit(s) | Name | R/W | Description |
---|---|---|---|
0 | TX_ENA | RW | Transmit enable. Set this bit to 1 to enable the transmit datapath. The MAC function clears this bit following a hardware or software reset. See the SW_RESET bit description. |
1 | RX_ENA | RW | Receive enable. Set this bit to 1 to enable the receive datapath. The MAC function clears this bit following a hardware or software reset. See the SW_RESET bit description. |
2 | XON_GEN | RW | Pause frame generation. When you set this bit to 1, the MAC function generates a pause frame with a pause quanta of 0, independent of the status of the receive FIFO buffer. |
3 | ETH_SPEED | RW | Ethernet speed
control.
When the MAC operates in gigabit mode, the eth_mode signal is asserted. This bit is not available in the small MAC variation. |
4 | PROMIS_EN | RW | Promiscuous enable. Set this bit to 1 to enable promiscuous mode. In this mode, the MAC function receives all frames without address filtering. |
5 | PAD_EN | RW | Padding removal on
receive. Set this bit to 1 to remove padding from receive frames before the MAC
function forwards the frames to the user application. This bit has no effect on
transmit frames.
This bit is not available in the small MAC variation. |
6 | CRC_FWD | RW | CRC forwarding on
receive.
|
7 | PAUSE_FWD | RW | Pause frame
forwarding on receive.
|
8 | PAUSE_IGNORE | RW | Pause frame
processing on receive.
|
9 | TX_ADDR_INS | RW | MAC address on
transmit.
|
10 | HD_ENA | RW | Half-duplex enable.
|
11 | EXCESS_COL | RO | Excessive collision
condition.
|
12 | LATE_COL | RO | Late collision
condition.
|
13 | SW_RESET | RW | Software reset. Set
this bit to 1 to trigger a software reset. The MAC function clears this bit
when it completes the software reset sequence.
When software reset is triggered, the MAC function completes the current transmission or reception, and subsequently disables the transmit and receive logic, flushes the receive FIFO buffer, and resets the statistics counters. |
14 | MHASH_SEL | RW | Hash-code mode
selection for multicast address resolution.
|
15 | LOOP_ENA | RW | Local loopback
enable. Set this bit to 1 to enable local loopback on the RGMII/GMII/MII of the
MAC. The MAC function sends transmit frames back to the receive path.
This bit is not available in the small MAC variation. |
18 – 16 | TX_ADDR_SEL[2:0] | RW | Source MAC address
selection on transmit. If you set the
TX_ADDR_INS bit to 1,
the value of these bits determines the MAC address the MAC function selects to
overwrite the source MAC address in frames received from the user application.
|
19 | MAGIC_ENA | RW | Magic packet
detection. Set this bit to 1 to enable magic packet detection.
This bit is not available in the small MAC variation. |
20 | SLEEP | RW | Sleep mode enable.
When the
MAGIC_ENA bit is 1,
set this bit to 1 to put the MAC function to sleep and enable magic packet
detection.
This bit is not available in the small MAC variation. |
21 | WAKEUP | RO | Node wake-up request.
Valid only when the
MAGIC_ENA bit is 1.
|
22 | XOFF_GEN | RW | Pause frame generation. Set this bit to 1 to generate a pause frame independent of the status of the receive FIFO buffer. The MAC function sets the pause quanta field in the pause frame to the value configured in the pause_quant register. |
23 | CNTL_FRM_ENA | RW | MAC control frame
enable on receive.
|
24 | NO_LGTH_CHECK | RW | Payload length check
on receive.
This bit is not available in the small MAC variation |
25 | ENA_10 | RW | 10-Mbps interface enable. Set this bit to 1 to enable the 10-Mbps interface. The MAC function asserts the ena_10 signal when you enable the 10-Mbps interface. You can also enable the 10-Mbps interface by asserting the set_10 signal. |
26 | RX_ERR_DISC | RW | Erroneous frames
processing on receive.
|
27 | DISABLE_READ_TIMEOUT | RW |
By default, this bit is set to 0. Set this bit to 1 to disable MAC configuration register read timeout. To ensure the configuration register does not wait for read timeout when an error occurs, set this bit to 1. |
28 – 30 | Reserved | — | — |
31 | CNT_RESET | RW | Statistics counters reset. Set this bit to 1 to clear the statistics counters. The MAC function clears this bit when the reset sequence completes. |
Statistics Counters (Dword Offset 0x18 – 0x38)
The following table describes the read-only registers that collect the statistics on the transmit and receive datapaths. A hardware reset clears these registers; a software reset also clears these registers except aMacID. The statistics counters roll up when the counter is full.
The register description uses the following definitions:
- Good frame—error-free frames with valid frame length.
- Error frame—frames that contain errors or whose length is invalid.
- Invalid frame—frames that are not addressed to the MAC function. The MAC function drops this frame.
Dword
Offset |
Name | R/W | Description |
---|---|---|---|
0x18 – 0x19 | aMacID | RO | The MAC address. This register is wired to the primary MAC address in the mac_0 and mac_1 registers. |
0x1A | aFramesTransmittedOK | RO | The number of frames that are successfully transmitted including the pause frames. |
0x1B | aFramesReceivedOK | RO | The number of frames that are successfully received including the pause frames. |
0x1C | aFrameCheck SequenceErrors | RO | The number of receive frames with CRC error. |
0x1D | aAlignmentErrors | RO | The number of receive frames with alignment error. |
0x1E | aOctetsTransmittedOK | RO | The number of data and
padding octets that are successfully transmitted.
This register contains the lower 32 bits of the aOctetsTransmittedOK counter. The upper 32 bits of this statistics counter reside at the dword offset 0x0F. |
0x1F | aOctetsReceivedOK | RO | The number of data and
padding octets that are successfully received.
The lower 32 bits of the aOctetsReceivedOK counter. The upper 32 bits of this statistics counter reside at the dword offset 0x3D. |
0x20 | aTxPAUSEMACCtrlFrames | RO | The number of pause frames transmitted. |
0x21 | aRxPAUSEMACCtrlFrames | RO | The number received pause frames received. |
0x22 | ifInErrors | RO | The number of errored frames received. |
0x23 | ifOutErrors | RO | The number of transmit
frames with one the following errors:
|
0x24 | ifInUcastPkts | RO | The number of valid unicast frames received. |
0x25 | ifInMulticastPkts | RO | The number of valid multicast frames received. The count does not include pause frames. |
0x26 | ifInBroadcastPkts | RO | The number of valid broadcast frames received. |
0x27 | ifOutDiscards | — | This statistics counter is
not in use.
The MAC function does not discard frames that are written to the FIFO buffer by the user application. |
0x28 | ifOutUcastPkts | RO | The number of valid unicast frames transmitted. |
0x29 | ifOutMulticastPkts | RO | The number of valid multicast frames transmitted, excluding pause frames. |
0x2A | ifOutBroadcastPkts | RO | The number of valid broadcast frames transmitted. |
0x2B | etherStatsDropEvents | RO | The number of frames that are dropped due to MAC internal errors when FIFO buffer overflow persists. |
0x2C | etherStatsOctets | RO | The total number of octets
received. This count includes both good and errored frames.
This register is the lower 32 bits of etherStatsOctets. The upper 32 bits of this statistics counter reside at the dword offset 0x3E. |
0x2D | etherStatsPkts | RO | The total number of good and errored frames received. |
0x2E | etherStatsUndersizePkts | RO | The number of frames received with length less than 64 bytes. This count does not include errored frames. |
0x2F | etherStatsOversizePkts | RO | The number of frames received that are longer than the value configured in the frm_length register. This count does not include errored frames. |
0x30 | etherStatsPkts64Octets | RO | The number of 64-byte frames received. This count includes good and errored frames. |
0x31 | etherStatsPkts65to127Octets | RO | The number of received good and errored frames between the length of 65 and 127 bytes. |
0x32 | etherStatsPkts128to255Octets | RO | The number of received good and errored frames between the length of 128 and 255 bytes. |
0x33 | etherStatsPkts256to511Octets | RO | The number of received good and errored frames between the length of 256 and 511 bytes. |
0x34 | etherStatsPkts512to1023Octets | RO | The number of received good and errored frames between the length of 512 and 1023 bytes. |
0x35 | etherStatsPkts1024to1518Octets | RO | The number of received good and errored frames between the length of 1024 and 1518 bytes. |
0x36 | etherStatsPkts1519toXOctets | RO | The number of received good and errored frames between the length of 1519 and the maximum frame length configured in the frm_length register. |
0x37 | etherStatsJabbers | RO | Too long frames with CRC error. |
0x38 | etherStatsFragments | RO | Too short frames with CRC error. |
0x39 | Reserved | — | Unused |
Extended Statistics Counters (0x3C – 0x3E) | |||
0x3C | msb_aOctetsTransmittedOK | RO | Upper 32 bits
of the respective statistics counters. By default all statistics
counters are 32 bits wide. These statistics counters can be extended
to 64 bits by turning on the Enable 64-bit byte counters parameter.
To read the counter, read the lower 32 bits first, then followed by the extended statistic counter bits. |
0x3D | msb_aOctetsReceivedOK | RO | |
0x3E | msb_etherStatsOctets | RO |
Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
The following table describes the registers that determine how the MAC function processes transmit and receive frames. A software reset does not change the values in these registers.
Dword
Offset |
Name | R/W | Description |
---|---|---|---|
0x3A | tx_cmd_stat | RW | Specifies how the MAC
function processes transmit frames. When you turn on the
Align packet headers to
32-bit boundaries option, this register resets to 0x00040000 upon a
hardware reset. Otherwise, it resets to 0x00.
|
0x3B | rx_cmd_stat | RW | Specifies how the MAC
function processes receive frames. When you turn on the
Align packet headers to
32-bit boundaries option, this register resets to 0x02000000 upon a
hardware reset. Otherwise, it resets to 0x00.
|
Supplementary Address (Dword Offset 0xC0 – 0xC7)
Dword
Offset |
Name | R/W | Description | HW Reset |
---|---|---|---|---|
0xC0 | smac_0_0 | RW | You can
specify up to four 6-byte supplementary addresses:
Map the supplementary addresses to the respective registers in the same manner as the primary MAC address. Refer to the description of mac_0 and mac_1. The MAC function uses the supplementary addresses for the following operations:
If you do not require the use of supplementary addresses, configure them to the primary address. |
0 |
0xC1 | smac_0_1 | |||
0xC2 | smac_1_0 | |||
0xC3 | smac_1_1 | |||
0xC4 | smac_2_0 | |||
0xC5 | smac_2_1 | |||
0xC6 | smac_3_0 | |||
0xC7 | smac_3_1 |
IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)
Dword Offset | Name | R/W | Description | HW Reset |
---|---|---|---|---|
0xD0 | tx_period | RW | Clock period for
timestamp adjustment on the transmit datapath. The period register is
multiplied by the number of stages separating actual timestamp and the GMII
bus.
The default value for the period is 0. For 125-MHz clock, set this register to 8 ns. |
0x0 |
0xD1 | tx_adjust_fns | RW | Static timing
adjustment in fractional nanoseconds for outbound timestamps on the transmit
datapath.
|
0x0 |
0xD2 | tx_adjust_ns | RW | Static timing
adjustment in nanoseconds for outbound timestamps on the transmit datapath.
|
0x0 |
0xD3 | rx_period | RW | Clock period for
timestamp adjustment on the receive datapath. The period register is multiplied
by the number of stages separating actual timestamp and the GMII bus.
The default value for the period is 0. For 125-MHz clock, set this register to 8 ns. |
0x0 |
0xD4 | rx_adjust_fns | RW | Static timing
adjustment in fractional nanoseconds for outbound timestamps on the receive
datapath.
|