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Intel FPGA Triple-Speed Ethernet IP Core User Guide

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UG-01008 | 2017.11.06

About This IP Core

The Intel^® FPGA Triple-Speed Ethernet IP core is a configurable intellectual property (IP) core that complies with the IEEE 802.3 standard.

It incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os. When offered in MAC-only mode, the IP connects with an external PHY chip using MII, GMII, or RGMII interface. The IP core was tested and successfully validated by the University of New Hampshire (UNH) interoperability lab.

Device Family Support

The IP core provides the following support for Intel^® FPGA device families.

Table 1. Intel FPGA IP Core Device Support Levels
Device Support Level	Definition
Preliminary	Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. This IP core can be used in production designs with caution.
Final	Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. This IP core is ready to be used in production designs.

Table 2. Device Family Support for Triple-Speed Ethernet MAC
Device Family	Support	Minimum Speed Grade with 1588 Feature
Intel^® Stratix^® 10	Preliminary	-I3
Stratix^® V	Final	-I3
Stratix^® IV	Final	Not supported
Intel^® Arria^® 10	Final	-I3
Arria^® V	Final	-I5
Arria^® II	Final	Not supported
Intel^® Cyclone^® 10 GX	Final	-I3
Intel^® Cyclone^® 10 LP	Final	Not supported
Cyclone^® V	Final	-I7
Cyclone^® IV	Final	Not supported
Intel^® MAX^® 10	Final	-I7

Features

Complete triple-speed Ethernet IP: 10/100/1000-Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA.
Successful validation from the University of New Hampshire (UNH) InterOperability Lab.
10/100/1000-Mbps Ethernet MAC features:
- Multiple variations: 10/100/1000-Mbps Ethernet MAC in full duplex, 10/100-Mbps Ethernet MAC in half duplex, 10/100-Mbps or 1000-Mbps small MAC (resource-efficient variant), and multiport MAC that supports up to 24 ports.
- Support for basic, VLAN, stacked VLAN, and jumbo Ethernet frames. Also supports control frames including pause frames.
- Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.
- Optional statistics counters.
MAC interfaces:
- Client side—8-bit or 32-bit Avalon^® Streaming (Avalon-ST)
- Network side—medium independent interface (MII), gigabit medium independent interface (GMII), or reduced gigabit medium independent interface (RGMII) on the network side. Optional loopback on these interfaces.
- Optional management data I/O (MDIO) master interface for PHY device management.
1000BASE-X/SGMII PCS features:
- Compliance with Clause 36 of the IEEE standard 802.3.
- Optional embedded PMA implemented with serial transceiver or LVDS I/O and soft CDR in Intel FPGA devices that support this interface at 1.25-Gbps data rate.
- Support for auto-negotiation as defined in Clause 37.
- Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and 1000BASE-T PHYs if the PHYs support SGMII.
PCS interfaces:
- Client side—MII or GMII
- Network side—ten-bit interface (TBI) for PCS without PMA; 1.25-Gbps serial interface for PCS with PMA implemented with serial transceiver or LVDS I/O and soft CDR in Intel FPGA devices that support this interface at 1.25-Gbps data rate.
Programmable features via 32-bit configuration registers:
- FIFO buffer thresholds.
- Pause quanta for flow control.
- Source and destination MAC addresses.
- Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.
- Promiscuous mode—receive frame filtering is disabled in this mode.
- Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants containing 1000BASE-X/SGMII PCS (with or without MAC), the frame length is up to 10 Kbytes.
- Optional auto-negotiation for the 1000BASE-X/SGMII PCS.
Error correction code protection feature for internal memory blocks.
Optional IEEE 1588v2 feature for 10/100/1000-Mbps Ethernet MAC with SGMII PCS and embedded serial PMA variation operating without internal FIFO buffer in full-duplex mode, 10/100/1000-Mbps MAC with SGMII PCS and embedded LVDS I/O, or MAC only variation operating without internal FIFO buffer in full-duplex mode. These features are supported in Intel^® Stratix^® 10, Arria^® V, Intel^® Arria^® 10, Intel^® Cyclone^® 10 GX, Cyclone^® V, Intel^® MAX^® 10, and Stratix^® V device families.

10/100/1000 Ethernet MAC Versus Small MAC

Table 3. Feature Comparison between 10/100/1000 Ethernet MAC and Small MAC
Feature	10/100/1000 Ethernet MAC	Small MAC
Speed	Triple speed (10/100/1000 Mbps)	10/100 Mbps or 1000 Mbps
External interfaces	MII/GMII or RGMII	MII only for 10/100 Mbps small MAC, GMII or RGMII for 1000 Mbps small MAC
Control interface registers	Fully programmable	Limited programmable options. The following options are fixed: Maximum frame length is fixed to 1518. Jumbo frames are not supported. FIFO buffer thresholds are set to fixed values. Store and forward option is not available. Interpacket gap is set to 12. Flow control is not supported; pause quanta is not in use. Checking of payload length is disabled. Supplementary MAC addresses are disabled. Padding removal is disabled. Sleep mode and magic packet detection is not supported.
Synthesis options	Fully configurable	Limited configurable options. The following options are NOT available: Flow control VLAN Statistics counters Multicast hash table Loopback TBI and 1.25 Gbps serial interface 8-bit wide FIFO buffers

High-Level Block Diagrams

High-level block diagrams of different variations of the Triple-Speed Ethernet IP core.

Figure 1. 10/100/1000-Mbps Ethernet MAC

Figure 2. Multi-port MAC

Figure 3. 10/100/1000-Ethernet MAC and 1000BASE-X/SGMII PCS with Optional PMA

Figure 4. 1000BASE-X/SGMII PCS with Optional PMA

Figure 5. Stand-Alone 10/100/1000 Mbps Ethernet MAC

Example Applications

This section shows example applications of different variations of the Triple-Speed Ethernet IP core.

The 10/100/1000-Gbps Ethernet MAC only variation can serve as a bridge between the user application and standard fast or gigabit Ethernet PHY devices.

Figure 6. Stand-Alone 10/100/1000 Mbps Ethernet MAC . Example application using this variation for a copper network.

When configured to include the 1000BASE-X/SGMII PCS function, the IP core can seamlessly connect to any industry standard gigabit Ethernet PHY device via a TBI. Alternatively, when the 1000BASE-X/SGMII PCS function is configured to include an embedded PMA, the IP core can connect directly to a gigabit interface converter (GBIC), small form-factor pluggable (SFP) module, or an SGMII PHY.

Figure 7. 10/100/1000 Mbps Ethernet MAC and 1000BASE-X PCS with Embedded PMA. Example application using the Triple-Speed Ethernet IP core with 1000BASE-X and PMA. The PMA block connects to an off-the-shelf GBIC or SFP module to communicate directly over the optical link.

Figure 8. 10/100/1000 Mbps Ethernet MAC and SGMII PCS with Embedded PMA—GMII/MII to 1.25-Gbps Serial Bridge Mode. Example application using the Triple-Speed Ethernet IP core with 1000BASE-X and PMA, in which the PCS function is configured to operate in SGMII mode and acts as a GMII-to-SGMII bridge. In this case, the transceiver I/O connects to an off-the-shelf Ethernet PHY that supports SGMII (10BASE-T, 100BASE-T, or 1000BASE-T Ethernet PHY).

IP Core Verification

For each release, Intel verifies the Triple-Speed Ethernet IP core through extensive simulation and internal hardware verification in various Intel FPGA device families. The University of New Hampshire (UNH) InterOperability Lab also successfully verified the IP core prior to its release.

Intel used a highly parameterizeable transaction-based testbench to test the following aspects of the IP core:

Register access
MDIO access
Frame transmission and error handling
Frame reception and error handling
Ethernet frame MAC address filtering
Flow control
Retransmission in half-duplex

Intel has also validated the Triple-Speed Ethernet IP core in both optical and copper platforms using the following development kits:

Nios^® II Development Kit, Cyclone^® II Edition (2C35)
Intel^® Arria^® 10 FPGA Development Kit
Intel^® Cyclone^® 10 LP FPGA Development Kit
Stratix^® III FPGA Development Kit
Stratix^® IV FPGA Development Kit
Stratix^® V FPGA Development Kit
Intel^® Stratix^® 10 FPGA Development Kit
Quad 10/100/1000 Marvell PHY
MorethanIP 10/100 and 10/100/1000 Ethernet PHY Daughtercards

Optical Platform

In the optical platform, the 10/100/1000 Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and PMA functions are instantiated.

The FPGA application implements the Ethernet MAC, the 1000BASE-X PCS, and an internal system using Ethernet connectivity. This internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an optical module is provided through an external SFP optical module. Certified 1.25 GBaud optical SFP transceivers are Finisar 1000BASE-SX FTLF8519P2BNL, Finisar 1000BASE-LX FTRJ-1319-3, and Avago Technologies AFBR-5710Z.

Copper Platform

In the copper platform, Intel FPGA tested the Triple-Speed Ethernet IP core with an external 1000BASE-T PHY devices. The IP core is connected to the external PHY device using MII, GMII, RGMII, and SGMII, in conjunction with the 1000BASE-X/SGMII PCS and PMA functions.

A 10/100/1000 Mbps Ethernet MAC and an internal system are implemented in the FPGA. The internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an Ethernet link is provided through a combined MII to an external PHY module. Certified 1.25 GBaud copper SFP transceivers are Finisar FCMJ-8521-3, Methode DM7041, and Avago Technologies ABCU-5700RZ.

Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet IP core are obtained by compiling the Triple-Speed Ethernet IP core using the Intel^® Quartus^® Prime software targeting a given device. The f_MAX of all configurations is more than 125 MHz.

Table 4. Intel^® Arria^® 10 Resource Utilization. The following estimates are obtained by targeting the Intel^® Arria^® 10 GX (10AX115R4F40I3SG) device with speed grade -3.
IP Core	Settings	FIFO Buffer Size (Bits)	Combinational ALUTs	Logic Registers	Memory (M20K)
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	2048x32	3643	5203	16
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	2048x8	3496	5105	11
10/100-Mbps Small MAC	MII. Full- and half-duplex.	2048x32	1501	2226	12
1000BASE-X/SGMII PCS	SGMII bridge enabled.	–	838	1188	2
	1000BASE-X. SGMII bridge enabled. PMA block (GXB).	–	759	1001	4
	1000BASE-X.	–	869	1238	0

Table 5. Arria^® II GX Resource Utilization. The following estimates are obtained by targeting the Arria^® II GX (EP2AGX260EF29I3) device with speed grade -3.
IP Core	Settings	FIFO Buffer Size (Bits)	Combinational ALUTs	Logic Registers	Memory (M9K Blocks/ M144K Blocks/MLAB Bits)
10/100/1000-Mbps Ethernet MAC	RGMII. All MAC options enabled. Full- and half-duplex.	2048x32	3357	3947	26/0/1828
1000BASE-X/SGMII PCS	1000BASE-X.	–	624	661	0/0/0
1000BASE-X/SGMII PCS	1000BASE-X. SGMII bridge enabled. PMA block (GXB).	–	1191	1214	1/0/160

Table 6. Intel^® Cyclone^® 10 GX Resource Utilization. The following estimates are obtained by targeting the Intel^® Cyclone^® 10 GX (10CX220YU484I6G) device with speed grade -3.
IP Core	Settings	FIFO Buffer Size (Bits)	Combinational ALUTs	Logic Registers	Memory (M20K)
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	2048x32	3858	5325	16
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	2048x8	3666	5125	11
10/100-Mbps Small MAC	MII. Full- and half-duplex.	2048x32	1441	2126	12
1000-Mbps Small MAC	GMII. Full-duplex only.	2048x32	1152	1894	10
1000BASE-X/SGMII PCS	SGMII bridge enabled.	–	851	1187	2
	1000BASE-X. SGMII bridge enabled. PMA block (GXB).	–	658	1006	2
	1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO).	–	658	1371	2

Table 7. Intel^® Cyclone^® 10 LP Resource Utilization. The following estimates are obtained by targeting the Intel^® Cyclone^® 10 LP (10CL120YF780I7G) device.
IP Core	Settings	FIFO Buffer Size (Bits)	Combinational ALUTs	Logic Registers	Memory (M9K)
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	2048x8	6724	4840	17
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	–	5863	4204	8
1000BASE-X/SGMII PCS	1000BASE-X. SGMII bridge enabled.	–	1628	1133	2
10/100-Mbps Small MAC	MII. Full and half-duplex only.	–	2416	1933	24
1000-Mbps Small MAC	GMII. Full-duplex only.	–	1998	1645	24

Table 8. Cyclone^® V Resource Utilization. The following estimates are obtained by targeting the Cyclone^® V GX (5CGXFC7C7F23C8) device with speed grade -8.
IP Core	Settings	FIFO Buffer Size (Bits)	Logic Elements	Logic Registers	Memory (M10K)
10/100/1000-Mbps Ethernet MAC	MII/GMII. Full- and half-duplex.	2048x32	3644	5340	27
10/100/1000-Mbps Ethernet MAC	MII/GMII. Full- and half-duplex.	2048x8	3489	5185	15
10/100-Mbps Small MAC	MII. Full- and half-duplex.	2048x32	1539	2295	21
1000-Mbps Small MAC	RGMII. Full-duplex only.	2048x32	1265	2060	20
1000BASE-X/SGMII PCS	SGMII bridge enabled	–	844	1241	2
	1000BASE-X. SGMII bridge enabled. PMA block (GXB).	–	656	947	9
	1000BASE-X. SGMII bridge enabled.	–	836	1097	9

Table 9. Cyclone^® IV GX Resource Utilization. The following estimates are obtained by targeting the Cyclone^® IV GX (EP4CGX150DF27C7) device with speed grade -7.
IP Core	Settings	FIFO Buffer Size (Bits)	Logic Elements	Logic Registers	Memory (M9K Blocks/ M144K Blocks/ MLAB Bits)
1000-Mbps Small MAC	RGMII Full-duplex only.	2048x32	2161	1699	24/0/0
10/100/1000-Mbps Ethernet MAC	MII/GMII Full- and half-duplex.	2048x32	5614	3666	31/0/0
1000BASE-X/SGMII PCS	1000BASE-X.	–	1149	661	0/0/0
1000BASE-X/SGMII PCS	1000BASE-X. SGMII bridge enabled. PMA block (GXB).	–	2001	1127	2/0/0

Table 10. Intel^® MAX^® 10 Resource Utilization. The following estimates are obtained by targeting the Intel^® MAX^® 10 (10M08DAF484C8G) device with speed grade -8.
IP Core	Settings	FIFO Buffer Size (Bits)	Logic Elements	Logic Registers	Memory (M9K)
10/100/1000-Mbps Ethernet MAC	MII/GMII. Full- and half-duplex.	2048x32	6806	4943	30
10/100/1000-Mbps Ethernet MAC	MII/GMII. Full- and half-duplex.	2048x8	6593	4767	17
10/100-Mbps Small MAC	MII. Full- and half-duplex.	2048x32	2650	2117	24
1000-Mbps Small MAC	RGMII Full-duplex only.	2048x32	2286	1862	24

Table 11. Intel^® Stratix^® 10 Resource Utilization. The following estimates are obtained by targeting the Intel^® Stratix^® 10 (1SG280HN3F43E3VG) device with speed grade -3.
IP Core	Settings	FIFO Buffer Size (Bits)	Combinational ALUTs	Logic Registers	Memory (M20K)
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	2048x32	3858	5325	16
10/100/1000-Mbps Ethernet MAC	MII/GMII. All MAC options enabled. Full- and half-duplex.	2048x8	3666	5125	11
10/100-Mbps Small MAC	MII. Full-duplex only.	2048x32	1283	2131	10
1000-Mbps Small MAC	GMII. Full-duplex only.	2048x32	1251	2112	10
1000BASE-X/SGMII PCS	SGMII bridge enabled.	–	907	1378	2
1000BASE-X/SGMII PCS	1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO).	–	925	1485	2

Table 12. Stratix^® V Resource Utilization. The following estimates are obtained by targeting the Stratix^® V GX (5SGXMA7N3F45C3) device with speed grade -3.
IP Core	Settings	FIFO Buffer Size (Bits)	Combinational ALUTs	Logic Registers	Memory   (M20K Blocks/ MLAB Bits)
10/100-Mbps Small MAC	MII. Full- and half-duplex.	2048x32	1261	2018	11/0
10/100-Mbps Small MAC	MII. All MAC options enabled.	2048x32	1261	2018	11/0
1000-Mbps Small MAC	GMII. All MAC options enabled.	2048x32	1227	1959	10/128
1000-Mbps Small MAC	RGMII. All MAC options enabled.	2048x32	1237	1984	10/128
10/100/1000-Mbps Ethernet MAC	MII/GMII. Full- and half-duplex.	—	3137	4298	5/2048
		2048x8	3627	4971	10/2048
		2048x32	3777	5145	16/2048
	MII/GMII. All MAC options enabled.	2048x32	3454	4928	16/768
	RGMII. All MAC options enabled.	2048x32	3466	4933	16/768
1000BASE-X/SGMII PCS	1000BASE-X.	–	614	786	0/0
	1000BASE-X. SGMII bridge enabled.	–	839	1160	0/480
	1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO).	–	857	1250	0/480
	1000BASE-X. SGMII bridge enabled. PMA block (GXB).	–	2203	1991	5/2208
	1000BASE-X. SGMII bridge enabled. PMA block (GXB). The reconfig controller is compiled with this variation.	–	1441	903	4/2048
10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS	All MAC options enabled. SGMII bridge enabled.	2048×32	4306	6132	16/1248
10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS	Default MAC options. SGMII bridge enabled. IEEE 1588v2 feature enabled.	0	5062	5318	4/1536

Table 13. Stratix^® IV Resource Utilization. The following estimates are obtained by targeting the Stratix^® IV GX (EP4SGX530NF45C4) device with speed grade -4.
IP Core	Settings	FIFO Buffer Size (Bits)	Combinational ALUTs	Logic Registers	Memory   (M9K Blocks/ M144K Blocks/MLAB Bits)
10/100-Mbps Small MAC	MII. Full- and half-duplex.	2048x32	1410	2127	12/1/1408
10/100-Mbps Small MAC	MII. All MAC options enabled.	2048x32	1157	1894	12/1/128
1000-Mbps Small MAC	GMII. All MAC options enabled.	2048x32	1160	1827	12/1/176
1000-Mbps Small MAC	RGMII. All MAC options enabled.	2048x32	1170	1861	12/1/176
10/100/1000-Mbps Ethernet MAC	MII/GMII. Full- and half-duplex.	–	2721	3395	0/0/3364
		2048x8	3201	3977	8/0/3620
		2048x32	3345	4425	12/1/3364
	MII/GMII. All MAC options enabled.	2048x32	3125	3994	12/1/2084
	RGMII. All MAC options enabled.	2048x32	3133	4021	12/1/2084
1000BASE-X/SGMII PCS	1000BASE-X.	–	624	661	0/0/0
	1000BASE-X. SGMII bridge enabled.	–	808	986	2/0/0
	1000BASE-X. SGMII bridge enabled. PMA block (LVDS_IO).	–	819	1057	2/0/0
	1000BASE-X. SGMII bridge enabled. PMA block (GXB).	–	1189	1212	1/0/160
10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS	All MAC options enabled. SGMII bridge enabled.	2048×32	3971	4950	14/1/2084

Release Information

Table 14. Triple-Speed Ethernet IP Core Release Information
Item	Description
Version	17.1
Release Date	November 2017
Ordering Code	Triple-Speed Ethernet: IP-TRIETHERNET IEEE 1588v2 for Triple-Speed Ethernet: IP-TRIETHERNETF
Product ID(s)	Triple-Speed Ethernet: 00BD IEEE 1588v2 for Triple-Speed Ethernet: 0104
Vendor ID(s)	6AF7

Intel verifies that the current version of the Intel^® Quartus^® Prime software compiles the previous version of each IP core. The Intel FPGA IP Release Notes report any exceptions to this verification. Intel does not verify compilation with IP core versions older than one release.

Getting Started with Intel FPGA IP Cores

Intel and strategic IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for Intel FPGA devices. The Intel^® Quartus^® Prime software installation includes the Intel FPGA IP library.

For more information on how to install and use Intel FPGA IP Cores, refer to the Introduction to Intel FPGA IP Cores.

Design Walkthrough

This walkthrough explains how to create a Triple-Speed Ethernet IP core design using Platform Designer in the Intel^® Quartus^® Prime software. After you generate a custom variation of the Triple-Speed Ethernet IP core, you can incorporate it into your overall project.

This walkthrough includes the following steps:

Creating a New Intel Quartus Prime Project

You need to create a new Intel^® Quartus^® Prime project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity.

To create a new project, follow these steps:

Launch the Intel^® Quartus^® Prime software on your PC. Alternatively, you can use the Intel^® Quartus^® Prime Lite Edition software.
On the File menu, click New Project Wizard.
In the New Project Wizard: Directory, Name, Top-Level Entity page, specify the working directory, project name, and top-level design entity name. Click Next.
In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include in the project.¹ Click Next.
In the New Project Wizard: Family & Device Settings page, select the device family and specific device you want to target for compilation. Click Next.
In the EDA Tool Settings page, select the EDA tools you want to use with the Intel^® Quartus^® Prime software to develop your project.
The last page in the New Project Wizard window shows the summary of your chosen settings. Click Finish to complete the Intel^® Quartus^® Prime project creation.

¹ To include existing files, you must specify the directory path to where you installed the IP core. You must also add the user libraries if you installed the IP Library in a different directory from where you installed the Intel^® Quartus^® Prime software.

Generating a Design Example or Simulation Model

After you have parameterized the IP core, you can also generate a design example, in addition to generating the IP core component files.

In the parameter editor, click Example Design to create a functional simulation model (design example that includes a testbench). The testbench and the automated script are located in the <variation name>_testbench directory.

Note: Generating a design example can increase processing time.

Note: Generate Example Design option only generates the design for functional simulation.

You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

Note: The dynamically generated design example for functional simulation is available only in Intel^® Arria^® 10, Intel^® Cyclone^® 10 GX, and Intel^® Stratix^® 10 devices.

Simulate the System

During system generation, Platform Designer generates a functional simulation model—or design example that includes a testbench—which you can use to simulate your system in any Intel FPGA-supported simulation tool.

Compiling the Triple-Speed Ethernet IP Core Design

Refer to Design Considerations chapter before compiling the Triple-Speed Ethernet IP core design.

To compile your design, click Start Compilation on the Processing menu in the Intel^® Quartus^® Prime software. You can use the generated .qip file to include relevant files into your project.

Programming an FPGA Device

After successfully compiling your design, program the targeted Intel FPGA device with the Intel^® Quartus^® Prime Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer to the Device Programming section in volume 3 of the Intel^® Quartus^® Prime Handbook.

Generated Files

The type of files generated in your project directory and their names may vary depending on the custom variation of the IP core you created.

Table 15. Generated Files
File Name	Description
<variation_name>.v or <variation_name>.vhd	A IP core variation file, which defines a VHDL or Verilog HDL top-level description of the custom IP core. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the Intel^® Quartus^® Prime software.
<variation_name>.bsf	Intel^® Quartus^® Prime symbol file for the IP core variation. You can use this file in the Intel^® Quartus^® Prime block diagram editor.
<variation_name>.qip and <variation_name>.sip	Contains Intel^® Quartus^® Prime project information for your IP core variations.
<variation_name>.cmp	A VHDL component declaration file for the IP core variation. Add the contents of this file to any VHDL architecture that instantiates the IP core.
<variation_name>.spd	Simulation Package Descriptor file. Specifies the files required for simulation.
Testbench Files (in <variation_name>_testbench folder)
README.txt	Read me file for the testbench design.
generate_sim.qpf and generate_sim.qsf	Dummy Intel^® Quartus^® Prime project and project setting file. Use this to start the Intel^® Quartus^® Prime in the correct directory to launch the generate_sim_verilog.tcl and generate_sim_vhdl.tcl files.
generate_sim_verilog.tcl and generate_sim_vhdl.tcl	A Tcl script to generate the DUT VHDL or Verilog HDL simulation model for use in the testbench.
/testbench_vhdl/<variation_name>/ <variation_name>_tb.vhd or /testbench_verilog/<variation_name>/ <variation_name>_tb.v	VHDL or Verilog HDL testbench that exercises your IP core variation in a third party simulator.
/testbench_vhdl/<variation_name>/run_ <variation_name>_tb.tcl or /testbench_verilog/<variation_name>/run_ <variation_name>_tb.tcl	A Tcl script for use with the ModelSim simulation software.
/testbench_vhdl/<variation_name>/ <variation_name>_wave.do or /testbench_verilog/<variation_name>/ <variation_name>_wave.do	A signal tracing macro script used with the ModelSim simulation software to display testbench signals.
/testbench_vhdl/models or /testbench_verilog/models	A directory containing VHDL and Verilog HDL models of the Ethernet generators and monitors used by the generated testbench.

Design Constraint File No Longer Generated

For a new Triple-Speed Ethernet IP core created using the Intel^® Quartus^® Prime software version 13.0 or later, the software no longer generate the <variation_name>_constraints.tcl file that contains the necessary constraints for the compilation of your IP core variation.

The following table lists the recommended Quartus pin assignments that you can set in your design.

Table 16. Recommended Quartus Pin Assignments
Pin Assignment	Assignment Value	Description	Design Pin
FAST_INPUT_REGISTER	ON	To optimize I/O timing for MII, GMII and TBI interface.	MII, GMII, RGMII, TBI input pins.
FAST_OUTPUT_REGISTER	ON	To optimize I/O timing for MII, GMII and TBI interface.	MII, GMII, RGMII, TBI output pins.
IO_STANDARD	1.4-V PCML or 1.5-V PCML	I/O standard for GXB serial input and output pins.	GXB transceiver serial input and output pins.
IO_STANDARD	LVDS	I/O standard for LVDS/IO serial input and output pins.	LVDS/IO transceiver serial input and output pins.
GLOBAL_SIGNAL	Global clock	To assign clock signals to use the global clock network. Use this setting to guide the Intel^® Quartus^® Prime software in the fitter process for better timing closure.	`clk` and `reset` pins for MAC only (without internal FIFO). `clk` and `ref_clk` input pins for MAC and PCS with transceiver (without internal FIFO).
GLOBAL_SIGNAL	Regional clock	To assign clock signals to use the regional clock network. Use this setting to guide the Intel^® Quartus^® Prime software in the fitter process for better timing closure.	`rx_clk <n>` and `tx_clk <n>` input pins for MAC only using MII/GMII interface (without internal FIFO). `rx_clk <n>` input pin for MAC only using RGMII interface (without internal FIFO).
GLOBAL_SIGNAL	OFF	To prevent a signal to be used as a global signal.	Signals for Arria^® V devices: `reset_ff_wr` and `reset_ff_rd` `*\| altera_tse_reset_synchronizer_chain_out`

Parameter Settings

You customize the Triple-Speed Ethernet IP core by specifying parameters using the Triple-Speed Ethernet parameter editor, launched from Platform Designer in the Intel^® Quartus^® Prime software. The customization enables specific core features during synthesis and generation.

This chapter describes the parameters and how they affect the behavior of the IP core. Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface.

Core Configuration

Table 17. Core Configuration Parameters
Name	Value	Description
Core Variation	10/100/1000 Mb Ethernet MAC 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS 1000BASE-X/SGMII PCS only 1000 Mb Small MAC 10/100 Mb Small MAC	Determines the primary blocks to include in the variation.
Enable ECC protection	On/Off	Turn on this option to enable ECC protection for internal memory blocks.
Interface	MII GMII RGMII MII/GMII	Determines the Ethernet-side interface of the MAC block. MII—The only option available for 10/100 Mb Small MAC core variations. GMII—Available only for 1000 Mb Small MAC core variations. RGMII—Available for 10/100/1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations. MII/GMII—Available only for 10/100/1000 Mb Ethernet MAC core variations. If this is selected, media independent interface (MII) is used for the 10/100 interface, and gigabit media independent interface (GMII) for the gigabit interface. Note: The RGMII interface is not supported in Intel^® Stratix^® 10, Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX devices from Intel^® Quartus^® Prime software version 17.1 onwards.
Use clock enable for MAC	On/Off	Turn on this option to include clock enable signals for the MAC. This option is only applicable for 10/100/1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations.
Use internal FIFO	On/Off	Turn on this option to include internal FIFO buffers in the core. You can only include internal FIFO buffers in single-port MACs.
Number of ports	1, 4, 8, 12, 16, 20, and 24	Specifies the number of Ethernet ports supported by the IP core. This parameter is enabled if the parameter Use internal FIFO is turned off. A multiport MAC does not support internal FIFO buffers. Note: For Intel^® Quartus^® Prime software version 17.1 onwards, the number of ports supported for Triple-Speed Ethernet designs targeting Intel^® Stratix^® 10, Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX devices is 8. This is applicable only when you select LVDS I/O for the Transceiver type option.
Transceiver type	None LVDS I/O GXB	This option is only available for variations that include the PCS block. None—the PCS block does not include an integrated transceiver module. The PCS block implements a ten-bit interface (TBI) to an external SERDES chip. LVDS I/O or GXB—the IP core includes an integrated transceiver module to implement a 1.25 Gbps transceiver. Respective GXB module is included for target devices with GX transceivers. For target devices with LVDS I/O including Soft-CDR such as Stratix^® III, the ALTLVDS module is included. The GXB option is not available in Intel^® Stratix^® 10 devices. GXB and LVDS I/O options are not available in Intel^® Cyclone^® 10 LP devices. Note: There may be a performance risk if you use the Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Intel^® Arria^® 10 devices for Intel^® Quartus^® Prime software version 17.0.2 and earlier. To avoid the performance risk, Intel^® recommends that you regenerate the Triple-Speed Ethernet IP core and recompile the design in the Intel^® Quartus^® Prime software version 17.1 or later. To download and install the software patch for Intel^® Quartus^® Prime version 17.0.2, refer to KDB link: Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 Devices.

Ethernet MAC Options

These options are enabled when your variation includes the MAC function. In small MACs, only the following options are available:

Enable MAC 10/100 half duplex support (10/100 Small MAC variations)
Align packet headers to 32-bit boundary (10/100 and 1000 Small MAC variations)

Table 18. MAC Options Parameters
Name	Value	Description
Ethernet MAC Options
Enable MAC 10/100 half duplex support	On/Off	Turn on this option to include support for half duplex operation on 10/100 Mbps connections.
Enable local loopback on MII/GMII/RGMII	On/Off	Turn on this option to enable local loopback on the MAC’s MII, GMII, or RGMII interface. If you turn on this option, the loopback function can be dynamically enabled or disabled during system operation via the MAC configuration register.
Enable supplemental MAC unicast addresses	On/Off	Turn on this option to include support for supplementary destination MAC unicast addresses for fast hardware-based received frame filtering.
Include statistics counters	On/Off	Turn on this option to include support for simple network monitoring protocol (SNMP) management information base (MIB) and remote monitoring (RMON) statistics counter registers for incoming and outgoing Ethernet packets. By default, the width of all statistics counters are 32 bits.
Enable 64-bit statistics byte counters	On/Off	Turn on this option to extend the width of selected statistics counters— `aOctetsTransmittedOK`, `aOctetsReceivedOK`, and `etherStatsOctets`—to 64 bits.
Include multicast hashtable	On/Off	Turn on this option to implement a hash table, a fast hardware-based mechanism to detect and filter multicast destination MAC address in received Ethernet packets.
Align packet headers to 32-bit boundary	On/Off	Turn on this option to include logic that aligns all packet headers to a 32-bit boundary. This helps reduce software overhead processing in realignment of data buffers. This option is available for MAC variations with 32 bits wide internal FIFO buffers and MAC variations without internal FIFO buffers. You must turn on this option if you intend to use the Triple-Speed Ethernet IP core with the Interniche TCP/IP protocol stack.
Enable full-duplex flow control	On/Off	Turn on this option to include the logic for full-duplex flow control that includes pause frames generation and termination.
Enable VLAN detection	On/Off	Turn on this option to include the logic for VLAN and stacked VLAN frame detection. When turned off, the MAC does not detect VLAN and staked VLAN frames. The MAC forwards these frames to the user application without processing them.
Enable magic packet detection	On/Off	Turn on this option to include logic for magic packet detection (Wake-on LAN).
MDIO Module
Include MDIO module (MDC/MDIO)	On/Off	Turn on this option if you want to access external PHY devices connected to the MAC function. When turned off, the core does not include the logic or signals associated with the MDIO interface.
Host clock divisor	—	Clock divisor to divide the MAC control interface clock to produce the MDC clock output on the MDIO interface. The default value is 40. For example, if the MAC control interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be specified. Intel recommends that the division factor is defined such that the MDC frequency does not exceed 2.5 MHz.

FIFO Options

The FIFO options are enabled only for MAC variations that include internal FIFO buffers.

Table 19. FIFO Options Parameters
Name	Value	Parameter
Width
Width	8 Bits and 32 Bits	Determines the data width in bits of the transmit and receive FIFO buffers.
Depth
Transmit	Between 64 and 64K	Determines the depth of the internal FIFO buffers.
Receive	Between 64 and 64K	Determines the depth of the internal FIFO buffers.

Timestamp Options

Table 20. Timestamp Options Parameters
Name	Value	Parameter
Timestamp
Enable timestamping	On/Off	Turn on this parameter to enable time stamping on the transmitted and received frames.
Enable PTP 1-step clock	On/Off	Turn on this parameter to insert timestamp on PTP messages for 1-step clock based on the TX Timestamp Insert Control interface. This parameter is disabled if you do not turn on Enable timestamping.
Timestamp fingerprint width	—	Use this parameter to set the width in bits for the timestamp fingerprint on the TX path. The default value is 4 bits.

PCS/Transceiver Options

The PCS/Transceiver options are enabled only if your core variation includes the PCS function.

Table 21. PCS/Transceiver Options Parameters
Name	Value	Parameter
PCS Options
PHY ID (32 bit)	—	Configures the PHY ID of the PCS block.
Enable SGMII bridge	On/Off	Turn on this option to add the SGMII clock and rate-adaptation logic to the PCS block. This option allows you to configure the PCS either in SGMII mode or 1000Base-X mode. If your application only requires 1000BASE-X PCS, turning off this option reduces resource usage. In Cyclone^® IV GX devices, `REFCLK[0,1]` and `REFCLK[4,5]` cannot connect directly to the GCLK network. If you enable the SGMII bridge, you must connect `ref_clk` to an alternative dedicated clock input pin.
Transceiver Options—apply only to variations that include GXB transceiver blocks
Export transceiver powerdown signal	On/Off	This option is not supported in Stratix^® V, Arria^® V, Arria^® V GZ, and Cyclone^® V devices. Turn on this option to export the powerdown signal of the GX transceiver to the top-level of your design. Powerdown is shared among the transceivers in a quad. Therefore, turning on this option in multiport Ethernet configurations maximizes efficient use of transceivers within the quad. Turn off this option to connect the powerdown signal internally to the PCS control register interface. This connection allows the host processor to control the transceiver powerdown in your system.
Enable transceiver dynamic reconfiguration	On/Off	This option is always turned on in devices other than Arria^® GX and Stratix^® II GX. When this option is turned on, the Intel^® FPGA IP core includes the dynamic reconfiguration signals. For designs targeting devices other than Arria^® V, Cyclone^® V, Stratix^® V, Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX, Intel recommends that you instantiate the ALTGX_RECONFIG megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. For Arria^® V, Cyclone^® V, and Stratix^® V designs, Intel recommends that you instantiate the Transceiver Reconfiguration Controller megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. The transceivers in the Arria^® V, Cyclone^® V, and Stratix^® V designs are configured with Intel FPGA Custom PHY IP core. The Custom PHY IP core require two reconfiguration interfaces for external reconfiguration controller. For more information on the reconfiguration interfaces required, refer to the V-Series Transceiver PHY IP Core User Guide and the respective device handbook. For more information about quad sharing considerations, refer to Sharing PLLs in Devices with GIGE PHY.
Starting channel number	0 – 284	Specifies the channel number for the GXB transceiver block. In a multiport MAC, this parameter specifies the channel number for the first port. Subsequent channel numbers are in four increments. In designs with multiple instances of GXB transceiver block (multiple instances of Triple-Speed Ethernet IP core with GXB transceiver block or a combination of Triple-Speed Ethernet IP core and other IP cores), Intel recommends that you set a unique starting channel number for each instance to eliminate conflicts when the GXB transceiver blocks share a transceiver quad. This option is not supported in Arria^® V, Cyclone^® V, Stratix^® V, Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX devices. For these devices, the channel numbers depends on the dynamic reconfiguration controller.
Series V GXB Transceiver Options
TX PLLs type	CMU ATX	This option is only available for variations that include the PCS block for Stratix^® V and Arria^® V GZ devices. Specifies the TX phase-locked loops (PLLs) type—CMU or ATX—in the GXB transceiver for Series V devices.
Enable SyncE Support	On/Off	Turn on this option to enable SyncE support by separating the TX PLL and RX PLL reference clock.
TX PLL clock network	x1 xN	This option is only available for variations that include the PCS block for Arria^® V and Cyclone^® V devices. Specifies the TX PLL clock network type.
Intel^® Arria^® 10 or Intel^® Cyclone^® 10 GX GXB Transceiver Options
Enable Intel^® Arria^® 10 or Intel^® Cyclone^® 10 GX transceiver dynamic reconfiguration	On/Off	Turn on this option for the Intel^® FPGA IP core to include the dynamic reconfiguration signals.

Note: You must configure the Intel^® Arria^® 10/ Intel^® Cyclone^® 10 GX Transceiver ATX PLL with an output clock frequency of 1250.0 MHz (instead of applying the default value of 625 MHz) when using the Intel^® Arria^® 10/ Intel^® Cyclone^® 10 GX Transceiver Native PHY with the Triple-Speed Ethernet IP core.

Refer to the respective device handbook for more information on dynamic reconfiguration in Intel FPGA devices.

Functional Description

The Triple-Speed Ethernet IP core includes the following functions:

10/100/1000 Ethernet MAC
1000BASE-X/SGMII PCS With Optional Embedded PMA
Intel FPGA IEEE 1588v2

10/100/1000 Ethernet MAC

The Intel 10/100/1000 Ethernet MAC function handles the flow of data between user applications and Ethernet network through an internal or external Ethernet PHY. Intel offers the following MAC variations:

Variations with internal FIFO buffers—supports only single port.
Variations without internal FIFO buffers—supports up to 24 ports (except for Intel^® Arria^® 10, Intel^® Cyclone^® 10 GX, and Intel^® Stratix^® 10 devices) and the ports can operate at different speeds.
Small MAC—provides basic functionalities of a MAC function using minimal resources.
Refer to 10/100/1000 Ethernet MAC Versus Small MAC for a feature comparison between the 10/100/1000 Ethernet MAC and small MAC.

The MAC function supports the following Ethernet frames: basic, VLAN and stacked VLAN, jumbo, and control frames.

MAC Architecture

Figure 9. 10/100/1000 Ethernet MAC With Internal FIFO Buffers

The FIFO buffers, which you can configure to 8- or 32-bits wide, store the transmit and receive data. The buffer width determines the data width on the Avalon-ST receive and transmit interfaces. You can configure the FIFO buffers to operate in cut-through or store-and-forward mode using the rx_section_full and tx_section_full registers.

Figure 10. Multiport MAC Without Internal FIFO Buffers

In a multiport MAC, the instances share the MDIO master and some configuration registers. You can use the Avalon-ST Multi-Channel Shared Memory FIFO core in Platform Designer to store the transmit and receive data.

Interfaces

The MAC function implements the following interfaces:

Avalon-ST on the system side.
- Avalon-ST sink port on transmit with the following properties:
  - Fixed data width, 8 bits, in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
  - Packet support using start-of-packet (SOP) and end-of-packet (EOP) signals, and partial final packet signals.
  - Error reporting.
  - Variable-length ready latency specified by the tx_almost_full register.
- Avalon-ST source port on receive with the following properties:
  - Fixed data width of 8 bits in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
  - Backpressure is supported only in MAC variations with internal FIFO buffers. Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds.
  - Packet support using SOP and EOP signals, and partial final packet signals.
  - Error reporting.
  - Ready latency is zero in MAC variations without internal FIFO buffers. In MAC variations with internal FIFO buffers, the ready latency is two.
Media independent interfaces on the network side—select MII, GMII, or RGMII by setting the Interface option on the Core Configuration page or the ETH_SPEED bit in the command_config register.
Control interface—an Avalon-MM slave port that provides access to 256 32-bit configuration and status registers, and statistics counters. This interface supports the use of waitrequest to stall the interconnect fabric for as many cycles as required.
PHY management interface—implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers. This interface supports up to 32 PHY devices.

MAC variations without internal FIFO buffers implement the following additional interfaces:

FIFO status interface—an Avalon-ST sink port that streams in the fill level of an external FIFO buffer. Only MAC variations without internal buffers implement this interface.
Packet classification interface—an Avalon-ST source port that streams out receive packet classification information. Only MAC variations without internal buffers implement this interface.

Transmit Datapath

On the transmit path, the MAC function accepts frames from a user application and constructs Ethernet frames before forwarding them to the PHY. Depending on the MAC configuration, the MAC function could perform the following tasks: realigns the payload, modifies the source address, calculates and appends the CRC-32 field, and inserts interpacket gap (IPG) bytes. In half-duplex mode, the MAC function also detects collision and attempts to retransmit frames when a collision occurs. The following conditions trigger transmission:

In MAC variations with internal FIFO buffers:
- Cut-through mode—transmission starts when the level of the FIFO level hits the transmit section-full threshold.
- Store and forward mode—transmission starts when a full packet is received.
In MAC variations without internal FIFO buffers, transmission starts as soon as data is available on the Avalon-ST transmit interface.

IP Payload Re-alignment

If you turn the Align packet headers to 32-bit boundaries option, the MAC function removes the additional two bytes from the beginning of Ethernet frames.

Address Insertion

By default, the MAC function retains the source address received from the user application. You can configure the MAC function to replace the source address with the primary MAC address or any of the supplementary addresses by setting the TX_ADDR_INS bit in the command_config register to 1. The TX_ADDR_SEL bits in the command_config register determines the address selection.

Frame Payload Padding

The MAC function inserts padding bytes (0x00) when the payload length does not meet the minimum length required:

46 bytes for basic frames
42 bytes for VLAN tagged frames
38 bytes for stacked VLAN tagged frames

CRC-32 Generation

To turn on CRC-32 generation, you must set the OMIT_CRC bit in the tx_cmd_stat register to 0 and send the frame to the MAC function with the ff_tx_crc_fwd signal deasserted.

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X ³² +X ²⁶ +X ²³ +X ²² +X ¹⁶ +X ¹² +X ¹¹ +X ¹⁰ +X ⁸ +X ⁷ +X ⁵ +X ⁴ +X ² +X ¹ +1

The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus transmitted in the following order: X31, X30,..., X1, X0.

Interpacket Gap Insertion

In full-duplex mode, the MAC function maintains the minimum number of IPG configured in the tx_ipg_length register between transmissions. You can configure the minimum IPG to any value between 64 and 216 bit times, where 64 bit times is the time it takes to transmit 64 bits of raw data on the medium.

In half-duplex mode, the MAC function constantly monitors the line. Transmission starts only when the line has been idle for a period of 96 bit times and any backoff time requirements have been satisfied. In accordance with the standard, the MAC function begins to measure the IPG when the m_rx_crs signal is deasserted.

Collision Detection in Half-Duplex Mode

Collision occurs only in a half-duplex network. It occurs when two or more nodes transmit concurrently. The PHY device asserts the m_rx_col signal to indicate collision.

When the MAC function detects collision during transmission, it stops the transmission and sends a 32-bit jam pattern instead. A jam pattern is a fixed pattern, 0x648532A6, and is not compared to the CRC of the frame. The probability of a jam pattern to be identical to the CRC is very low, 0.532%.

If the MAC function detects collision while transmitting the preamble or SFD field, it sends the jam pattern only after transmitting the SFD field, which subsequently results in a minimum of 96-bit fragment.

If the MAC function detects collision while transmitting the first 64 bytes, including the preamble and SFD fields, the MAC function waits for an interval equal to the backoff period and then retransmits the frame. The frame is stored in a 64-byte retransmit buffer. The backoff period is generated from a pseudo-random process, truncated binary exponential backoff.

Figure 11. Frame Retransmission

The backoff time is a multiple of slot times. One slot is equal to a 512 bit times period. The number of the delay slot times, before the Nth retransmission attempt, is chosen as a uniformly distributed random integer in the following range:

0 ≤ r < 2k

k = min( n , N ), where n is the number of retransmissions and N = 10.

For example, after the first collision, the backoff period, in slot time, is 0 or 1. If a collision occurs during the first retransmission, the backoff period, in slot time, is 0, 1, 2, or 3.

The maximum backoff time, in 512 bit times slots, is limited by N set to 10 as specified in the IEEE Standard 802.3.

If collision occurs after 16 consecutive retransmissions, the MAC function reports an excessive collision condition by setting the EXCESS_COL bit in the command_config register to 1, and discards the current frame from the transmit FIFO buffer.

In networks that violate standard requirements, collision may occur after the transmission of the first 64 bytes. If this happens, the MAC function stops transmitting the current frame, discards the rest of the frame from the transmit FIFO buffer, and resumes transmitting the next available frame. You can check the LATE_COL register (command_config [12]) to verify if the MAC has discarded any frame due to collision.

Receive Datapath

The MAC function receives Ethernet frames from the network via a PHY and forwards the payload with relevant frame fields to the user application after performing checks, filtering invalid frames, and removing the preamble and SFD.

Preamble Processing

The MAC function uses the SFD (0xD5) to identify the last byte of the preamble. If an SFD is not found after the seventh byte, the MAC function rejects the frame and discards it.

The IEEE standard specifies that frames must be separated by an interpacket gap (IPG) of at least 96 bit times. The MAC function, however, can accept frames with an IPG of less than 96 bit times; at least 8-bytes and 6-bytes in RGMII/GMII (1000 Mbps operation) and RGMII/MII (10/100 Mbps operation) respectively.

The MAC function removes the preamble and SFD fields from valid frames.

Collision Detection in Half-Duplex Mode

In half-duplex mode, the MAC function checks for collisions during frame reception. When collision is detected during the reception of the first 64 bytes, the MAC function discards the frame if the RX_ERR_DISC bit is set to 1. Otherwise, the MAC function forwards the frame to the user application with error.

Address Checking

The MAC function can accept frames with the following address types:

Unicast address—bit 0 of the destination address is 0.
Multicast address—bit 0 of the destination address is 1.
Broadcast address—all 48 bits of the destination address are 1.
The MAC function always accepts broadcast frames. If promiscuous mode is enabled (PROMIS_EN bit in the command_config register = 1), the MAC function omits address filtering and accepts all frames.

Unicast Address Checking

When promiscuous mode is disabled, the MAC function only accepts unicast frames if the destination address matches any of the following addresses:

The primary address, configured in the registers mac_0 and mac_1
The supplementary addresses, configured in the following registers: smac_0_0/smac_0_1, smac_1_0/smac_1_1, smac_2_0/smac_2_1 and smac_3_0/smac_3_1
Otherwise, the MAC function discards the frame.

Multicast Address Resolution

You can use either a software program running on the host processor or a hardware multicast address resolution engine to resolve multicast addresses. Address resolution using a software program can affect the system performance, especially in gigabit mode.

The MAC function uses a 64-entry hash table in the register space, multicast hash table, to implement the hardware multicast address resolution engine as shown in figure below. The host processor must build the hash table according to the specified algorithm. A 6-bit code is generated from each multicast address by XORing the address bits as shown in table below. This code represents the address of an entry in the hash table. Write one to the most significant bit in the table entry. All multicast addresses that hash to the address of this entry are valid and accepted.

You can choose to generate the 6-bit code from all 48 bits of the destination address by setting the MHASH_SEL bit in the command_config register to 0, or from the lower 24 bits by setting the MHASH_SEL bit to 1. The latter option is provided if you want to omit the manufacturer's code, which typically resides in the upper 24 bits of the destination address, when generating the 6-bit code.

Figure 12. Hardware Multicast Address Resolution Engine

Table 22. Hash Code Generation—Full Destination Address. Algorithm for generating the 6-bit code from the entire destination address.
Hash Code Bit	Value
0	`xor` multicast MAC address bits 7:0
1	`xor` multicast MAC address bits 15:8
2	`xor` multicast MAC address bits 23:16
3	`xor` multicast MAC address bits 31:24
4	`xor` multicast MAC address bits 39:32
5	`xor` multicast MAC address bits 47:40

Table 23. Hash Code Generation—Lower 24 Bits of Destination Address. Algorithm for generating the 6-bit code from the lower 24 bits of the destination address.
Hash Code Bit	Value
0	`xor` multicast MAC address bits 3:0
1	`xor` multicast MAC address bits 7:4
2	`xor` multicast MAC address bits 11:8
3	`xor` multicast MAC address bits 15:12
4	`xor` multicast MAC address bits 19:16
5	`xor` multicast MAC address bits 23:20

The MAC function checks each multicast address received against the hash table, which serves as a fast matching engine, and a match is returned within one clock cycle. If there is no match, the MAC function discards the frame.

All multicast frames are accepted if all entries in the hash table are one.

Frame Type Validation

The MAC function checks the length/type field to determine the frame type:

Length/type < 0x600—the field represents the payload length of a basic Ethernet frame. The MAC function continues to check the frame and payload lengths.
Length/type >= 0x600—the field represents the frame type.
- Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC function continues to check the frame and payload lengths, and asserts the following signals:
  - for VLAN frames, rx_err_stat[16] in MAC variations with internal FIFO buffers or pkt_class_data[1] in MAC variations without internal FIFO buffers
  - for stacked VLAN frames, rx_err_stat[17] in MAC variations with internal FIFO buffers or pkt_class_data[0] in MAC variations without internal FIFO buffers.
- Length/type = 0x8088—control frames. The next two bytes, the Opcode field, indicate the type of control frame.
  - For pause frames (Opcode = 0x0001), the MAC function continues to check the frame and payload lengths. For valid pause frames, the MAC function proceeds with pause frame processing. The MAC function forwards pause frames to the user application only when the PAUSE_FWD bit in the command_config register is set to 1.
  - For other types of control frames, the MAC function accepts the frames and forwards them to the user application only when the CNTL_FRM_ENA bit in the command_config register is set to 1.
For other field values, the MAC function forwards the receive frame to the user application.

Payload Pad Removal

You can turn on padding removal by setting the PAD_EN bit in the command_config register to 1. The MAC function removes the padding, prior to forwarding the frames to the user application, when the payload length is less than the following values for the different frame types:

46 bytes for basic MAC frames
42 bytes for VLAN tagged frames
38 bytes for stacked VLAN tagged frames

When padding removal is turned off, complete frames including the padding are forwarded to the Avalon-ST receive interface.

CRC Checking

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X ³² +X ²⁶ +X ²³ +X ²² +X ¹⁶ +X ¹² +X ¹¹ +X ¹⁰ +X ⁸ +X ⁷ +X ⁵ +X ⁴ +X ² +X ¹ +1

The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC bits are thus received in the following order: X31, X30,..., X1, X0.

If the MAC function detects CRC-32 error, it marks the frame invalid by asserting the following signals:

rx_err[2] in MAC variations with internal FIFO buffers.
data_rx_error[1] in MAC variations without internal FIFO buffers.

The MAC function discards frames with CRC-32 error if the RX_ERR_DISC bit in the command_config register is set to 1.

For frames less than the required minimum length, the MAC function forwards the CRC-32 field to the user application if the CRC_FWD and PAD_EN bits in the command_config register are 1 and 0 respectively. Otherwise, the CRC-32 field is removed from the frame.

Length Checking

The MAC function checks the frame and payload lengths of basic, VLAN tagged, and stacked VLAN tagged frames.

The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the different frame types:

Basic frames—the value specified in the frm_length register
VLAN tagged frames—the value specified in the frm_length register plus four
Stacked VLAN tagged frames—the value specified in the frm_length register plus eight

To prevent FIFO buffer overflow, the MAC function truncates the frame if it is more than 11 bytes longer than the allowed maximum length.

For frames of a valid length, the MAC function continues to check the payload length if the NO_LGTH_CHECK bit in the command_config register is set to 0. The MAC function keeps track of the payload length as it receives a frame, and checks the length against the length/type field in basic MAC frames or the client length/type field in VLAN tagged frames. The payload length is valid if it satisfies the following conditions:

The actual payload length matches the value in the length/type or client length/type field.
Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.
VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.
Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding 1536.

If the frame or payload length is not valid, the MAC function asserts one of the following signals to indicate length error:

rx_err[1] in MACs with internal FIFO buffers.
data_rx_error[0] in MACs without internal FIFO buffers.

Frame Writing

The IP core removes the preamble and SFD fields from the frame. The CRC field and padding bytes may be removed depending on the configuration.

For MAC variations with internal FIFO buffers, the MAC function writes the frame to the internal receive FIFO buffers.For MAC variations without internal FIFO buffers, it forwards the frame to the Avalon-ST receive interface.

MAC variations without internal FIFO buffers do not support backpressure on the Avalon-ST receive interface. In this variation, if the receiving component is not ready to receive data from the MAC function, the frame gets truncated with error and subsequent frames are also dropped with error.

IP Payload Alignment

The network stack makes frequent use of the IP addresses stored in Ethernet frames. When you turn on the Align packet headers to 32-bit boundaries option, the MAC function aligns the IP payload on a 32-bit boundary by adding two bytes to the beginning of Ethernet frames. The padding of Ethernet frames are determined by the registers tx_cmd_stat and rx_cmd_stat on transmit and receive, respectively.

Table 24. 32-Bit Interface Data Structure — Non-IP Aligned Ethernet Frame
Bits
31...24	23...16	15...8	7...0
Byte 0	Byte 1	Byte 2	Byte 3
Byte 4	Byte 5	Byte 6	Byte 7

Table 25. 32-Bit Interface Data Structure — IP Aligned Ethernet Frame
Bits
31...24	23...16	15...8	7...0
padded with zeros		Byte 0	Byte 1
Byte 2	Byte 3	Byte 4	Byte 5

MAC Transmit and Receive Latencies

Intel uses the following definitions for the transmit and receive latencies:

Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon-ST interface.
Receive latency is the number of clock cycles the MAC function takes to present the first bit on the Avalon-ST interface after the bit was received on the network-side interface (MII/GMII/RGMII).

Table 26. Transmit and Receive Nominal Latency. The transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the typical values specified in this user guide when deriving the latencies.
MAC Configuration	Latency (Clock Cycles) ² ³
MAC Configuration	Transmit	Receive
MAC with Internal FIFO Buffers ⁴
GMII in cut-through mode	32	110
MII in cut-through mode	41	218
RGMII in gigabit and cut-through mode	33	113
RGMII in 10/100 Mbps and cut-through mode	42	221
MAC without Internal FIFO Buffers ⁵
GMII	11	37
MII	22	77
RGMII in gigabit mode	12	40
RGMII in10/100 Mbps	23	80

² The clocks in all domains are running at the same frequency.

³ The numbers in this table are from simulation.

⁴ The data width is set to 32 bits

⁵ The data width is set to 8 bits.

FIFO Buffer Thresholds

For MAC variations with internal FIFO buffers, you can change the operations of the FIFO buffers, and manage potential FIFO buffer overflow or underflow by configuring the following thresholds:

Almost empty
Almost full
Section empty
Section full

These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers. The FIFO buffer thresholds are configured via the registers.

Receive Thresholds

Figure 13. Receive FIFO Thresholds

Table 27. Receive Thresholds
Threshold	Register Name	Description
Almost empty	`rx_almost_empty`	The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the `ff_rx_a_empty` signal. The MAC function stops reading from the FIFO buffer and subsequently stops transferring data to the user application to avoid buffer underflow. When the MAC function detects an EOP, it transfers all data to the user application even if the number of unread entries is below this threshold.
Almost full	`rx_almost_full`	The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the `ff_rx_a_full` signal. If the user application is not ready to receive data (`ff_rx_rdy` = 0), the MAC function performs the following operations: Stops writing data to the FIFO buffer. Truncates received frames to avoid FIFO buffer overflow. Asserts the `rx_err[0]` signal when the `ff_rx_eop` signal is asserted. Marks the truncated frame invalid by setting the `rx_err[3]` signal to 1. If the `RX_ERR_DISC` bit in the `command_config` register is set to 1 and the section-full (`rx_section_full`) threshold is set to 0, the MAC function discards frames with error received on the Avalon-ST interface.
Section empty	`rx_section_empty`	An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer hits this threshold, the MAC function generates an XOFF pause frame to indicate FIFO congestion to the remote Ethernet device. When the FIFO level goes below this threshold, the MAC function generates an XON pause frame to indicate its readiness to receive new frames. To avoid data loss, you can use this threshold as an early warning to the remote Ethernet device on the potential FIFO buffer congestion before the buffer level hits the almost-full threshold. The MAC function truncates receive frames when the buffer level hits the almost-full threshold.
Section full	`rx_section_full`	The section-full threshold indicates that there are sufficient entries in the FIFO buffer for the user application to start reading from it. The MAC function asserts the `ff_rx_dsav` signal when the buffer level hits this threshold. Set this threshold to 0 to enable store and forward on the receive datapath. In the store and forward mode, the `ff_rx_dsav` signal remains deasserted. The MAC function asserts the `ff_rx_dval` signal as soon as a complete frame is written to the FIFO buffer.

Transmit Thresholds

Figure 14. Transmit FIFO Thresholds

Table 28. Transmit Thresholds
Threshold	Register Name	Description
Almost empty	`tx_almost_empty`	The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the `ff_tx_a_empty` signal. The MAC function stops reading from the FIFO buffer and sends the Ethernet frame with GMII / MII/ RGMII error to avoid FIFO underflow.
Almost full	`tx_almost_full`	The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the `ff_tx_a_full` signal. The MAC function deasserts the `ff_tx_rdy` signal to backpressure the Avalon-ST transmit interface.
Section empty	`tx_section_empty`	An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer reaches this threshold, the MAC function deasserts the `ff_tx_septy` signal. This threshold can serve as a warning about potential FIFO buffer congestion.
Section full	`tx_section_full`	This threshold indicates that there are sufficient entries in the FIFO buffer to start frame transmission. Set this threshold to 0 to enable store and forward on the transmit path. When you enable the store and forward mode, the MAC function forwards each frame as soon as it is completely written to the transmit FIFO buffer.

Transmit FIFO Buffer Underflow

If the transmit FIFO buffer hits the almost-empty threshold during transmission and the FIFO buffer does not contain the end-of-packet indication, the MAC function stops reading data from the FIFO buffer and initiates the following actions:

The MAC function asserts the RGMII/GMII/MII error signals (tx_control/gm_tx_err/m_tx_err) to indicate that the fragment transferred is not valid.
The MAC function deasserts the RGMII/GMII/MII transmit enable signals (tx_control/gm_tx_en/m_tx_en) to terminate the frame transmission.
After the underflow, the user application completes the frame transmission.
The transmitter control discards any new data in the FIFO buffer until the end of frame is reached.
The MAC function starts to transfer data on the RGMII/GMII/MII when the user application sends a new frame with an SOP.

Figure 15. Transmit FIFO Buffer Underflow. Figure illustrates the FIFO buffer underflow protection algorithm for gigabit Ethernet system.

Congestion and Flow Control

In full-duplex mode, the MAC function implements flow control to manage the following types of congestion:

Remote device congestion—the receiving device experiences congestion and requests the MAC function to stop sending data.
Receive FIFO buffer congestion—when the receive FIFO buffer is almost full, the MAC function sends a pause frame to the remote device requesting the remote device to stop sending data.
Local device congestion—any device connected to the MAC function, such as a processor, can request the remote device to stop data transmission.

Remote Device Congestion

When the MAC function receives an XOFF pause frame and the PAUSE_IGNORE bit in the command_config register is set to 0, the MAC function completes the transfer of the current frame and stops transmission for the amount of time specified by the pause quanta in 512 bit times increments. Transmission resumes when the timer expires or when the MAC function receives an XON frame.

You can configure the MAC function to ignore pause frames by setting the PAUSE_IGNORE bit in the command_config register is set to 1.

Receive FIFO Buffer and Local Device Congestion

Pause frames generated are compliant to the IEEE Standard 802.3 annex 31A & B. The MAC function generates pause frames when the level of the receive FIFO buffer hits a level that can potentially cause an overflow, or at the request of the user application. The user application can trigger the generation of an XOFF pause frame by setting the XOFF_GEN bit in the command_config register to 1 or asserting the xoff_gen signal.

For MAC variations with internal FIFO buffers, the MAC function generates an XOFF pause frame when the level of the FIFO buffer reaches the section-empty threshold (rx_section_empty). If transmission is in progress, the MAC function waits for the transmission to complete before generating the pause frame. The fill level of an external FIFO buffer is obtained via the Avalon-ST receive FIFO status interface.

When generating a pause frame, the MAC function fills the pause quanta bytes P1 and P2 with the value configured in the pause_quant register. The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers, and the destination address is set to a fixed multicast address, 01-80-C2-00-00-01 (0x010000c28001).

The MAC function automatically generates an XON pause frame when the FIFO buffer section-empty flag is deasserted and the current frame transmission is completed. The user application can trigger the generation of an XON pause frame by clearing the XOFF_GEN bit and signal, and subsequently setting the XON_GEN bit to 1 or asserting the XON_GEN signal.

When generating an XON pause frame, the MAC function fills the pause quanta (payload bytes P1 and P2) with 0x0000 (zero quanta). The source address is set to the primary MAC address configured in the mac_0 and mac_1 registers and the destination address is set to a fixed multicast address, 01-80-C2-00-00-01 (0x010000c28001).

In addition to the flow control mechanism, the MAC function prevents an overflow by truncating excess frames. The status bit, rx_err[3], is set to 1 to indicate such errors. The user application should subsequently discard these frames by setting the RX_ERR_DISC bit in the command_config register to 1.

Magic Packets

A magic packet can be a unicast, multicast, or broadcast packet which carries a defined sequence in the payload section. Magic packets are received and acted upon only under specific conditions, typically in power-down mode.

The defined sequence is a stream of six consecutive 0xFF bytes followed by a sequence of 16 consecutive unicast MAC addresses. The unicast address is the address of the node to be awakened.

The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header, optional padding and CRC.

Sleep Mode

You can only put a node to sleep (set SLEEP bit in the command_config register to 1 and deassert the magic_sleep_n signal) if magic packet detection is enabled (set the MAGIC_ENA bit in the command_config register to 1).

Intel recommends that you do not put a node to sleep if you disable magic packet detection.

Network transmission is disabled when a node is put to sleep. The receiver remains enabled, but it ignores all traffic from the line except magic packets to allow a remote agent to wake up the node. In the sleep mode, only etherStatsPkts and etherStatsOctets count the traffic statistics.

Magic Packet Detection

Magic packet detection wakes up a node that was put to sleep. The MAC function detects magic packets with any of the following destination addresses:

Any multicast address
A broadcast address
The primary MAC address configured in the mac_0 and mac_1 registers
Any of the supplementary MAC addresses configured in the following registers if they are enabled: smac_0_0, smac_0_1, smac_1_0, smac_1_1, smac_2_0, smac_2_1, smac_3_0 and smac_3_1

When the MAC function detects a magic packet, the WAKEUP bit in the command_config register is set to 1, and the etherStatsPkts and etherStatsOctets statistics registers are incremented.

Magic packet detection is disabled when the SLEEP bit in the command_config register is set to 0. Setting the SLEEP bit to 0 also resets the WAKEUP bit to 0 and resumes the transmit and receive operations.

Local Loopback

You can enable local loopback on the MII/GMII/RGMII of the MAC function to exercise the transmit and receive paths. If you enable local loopback, use the same clock source for both the transmit and receive clocks. If you use different clock sources, ensure that the difference between the transmit and receive clocks is less than ±100 ppm.

To enable local loopback:

Initiate software reset by setting the SW_RESET bit in command_config register to 1.

Software reset disables the transmit and receive operations, flushes the internal FIFOs, and clears the statistics counters. The SW_RESET bit is automatically cleared upon completion.
When software reset is complete, enable local loopback on the MAC's MII/GMII/RGMII by setting the LOOP_ENA bit in command_config register to 1.
Enable transmit and receive operations by setting the TX_ENA and RX_ENA bits in command_config register to 1.
Initiate frame transmission.
Compare the statistics counters aFramesTransmittedOK and aFramesReceivedOK to verify that the transmit and receive frame counts are equal.
Check the statistics counters ifInErrorsand ifOutErrors to determine the number of packets transmitted and received with errors.
To disable loopback, initiate a software reset and set the LOOP_ENA bit in command_config register to 0.

MAC Error Correction Code (ECC)

The error correction code (ECC) feature is implemented to the memory instances in the IP core. This feature is capable of detecting single and double bit errors, and can fix single bit errors in the corrupted data.

Note: This feature is only applicable for Stratix^® V and Intel^® Arria^® 10 devices.

Table 29. Core Variation and ECC Protection Support
Core Variation	ECC Protection Support
10/100/1000 Mb Ethernet MAC	Protects the following options: transmit and receive FIFO buffer Retransmit buffer (if half duplex is enabled) Statistic counters (if enabled) Multicast hashtable (if enabled)
10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS	Protects the following options: transmit and receive FIFO buffer Retransmit buffer (if half duplex is enabled) Statistic counters (if enabled) Multicast hashtable (if enabled) SGMII bridge (if enabled)
1000BASE-X/SGMII PCS only	Protects the SGMII bridge (if enabled)
1000 Mb Small MAC	Protects the transmit and receive FIFO buffer
10/100 Mb Small MAC	Protects the following options: transmit and receive FIFO buffer Retransmit buffer (if half duplex is enabled)

When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and 1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the IP core.

Single channel core configuration—eccstatus[1:0] output ports.
Multi-channel core configuration—eccstatus_<n>[1:0] output ports, where eccstatus_0[1:0] is for channel 0, eccstatus_1[1:0] for channel 1, and so on.

MAC Reset

A hardware reset resets all logic. A software reset only disables the transmit and receive paths, clears all statistics registers, and flushes the receive FIFO buffer. The values of configuration registers, such as the MAC address and thresholds of the FIFO buffers, are preserved during a software reset.

When you trigger a software reset, the MAC function sets the TX_ENA and RX_ENA bits in the command_config register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only disabled when the current frame transmission and reception complete.

To trigger a hardware reset, assert the reset signal.
To trigger a software reset, set the SW_RESET bit in the command_config register to 1. The SW_RESET bit is cleared automatically when the software reset ends.

Intel recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating speed or mode without changing other configurations, preserve the command_config register before performing the software reset and restore the register after the changing the MAC operating speed or mode.

Figure 16. Software Reset Sequence

Note: If the SW_RESET bit is 1 when the line clocks are not available (for example, cable is disconnected), the statistics registers may not be cleared.

PHY Management (MDIO)

This module implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers, and supports up to 32 PHY devices.

To access each PHY device, write the PHY address to the MDIO register (mdio_addr0/1) followed by the transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the MDIO registers via the Avalon-MM interface.

For more information about the registers of a PHY device, refer to the specification provided with the device.

For more information about the MDIO registers, refer to MAC Configuration Register Space.

MDIO Connection

Figure 17. MDIO Interface

MDIO Frame Format

The MDIO master communicates with the slave PHY device using MDIO frames. A complete frame is 64 bits long and consists of 32-bit preamble, 14-bit command, 2-bit bus direction change, and 16-bit data. Each bit is transferred on the rising edge of the MDIO clock, mdc.

Table 30. MDIO Frame Formats (Read/Write). Field settings for MDIO transactions.
Type	PRE	Command
Type	PRE	ST MSB LSB	OP MSB LSB	Addr1 MSB LSB	Addr2 MSB LSB	TA	Data MSB LSB	Idle
Read	1 ... 1	01	10	xxxxx	xxxxx	Z0	xxxxxxxxxxxxxxxx	Z
Write	1 ... 1	01	01	xxxxx	xxxxx	10	xxxxxxxxxxxxxxxx	Z

Table 31. MDIO Frame Field Descriptions
Name	Description
PRE	Preamble. 32 bits of logical 1 sent prior to every transaction.
ST	Start indication. Standard MDIO (Clause 22): 0b01.
OP	Opcode. Defines the transaction type.
Addr1	The PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, the Addr1 field is set to the value configured in the `mdio_addr0` register. For PHY device 1, the Addr1 field is set to the value configured in the `mdio_addr1` register.
Addr2	Register Address. Each PHY can have up to 32 registers.
TA	Turnaround time. Two bit times are reserved for read operations to switch the data bus from write to read for read operations. The PHY device presents its register contents in the data phase and drives the bus from the 2^nd bit of the turnaround phase.
Data	16-bit data written to or read from the PHY device.
Idle	Between frames, the MDIO data signal is tri-stated.

Connecting MAC to External PHYs

The MAC function implements a flexible network interface—MII for 10/100-Mbps interfaces, RGMII or GMII for 1000-Mbps interfaces—that you can use in multiple applications. This section provides the guidelines for implementing the following network applications:

Gigabit Ethernet operation
Programmable 10/100 Ethernet operation
Programmable 10/100/1000 Ethernet operation

Gigabit Ethernet

You can connect gigabit Ethernet PHYs to the MAC function via GMII or RGMII. On the receive path, connect the 125-MHz clock provided by the PHY device to the MAC clock, rx_clk. On transmit, drive a 125-MHz clock to the PHY GMII or RGMII. Connect a 125-MHz clock source to the MAC transmit clock, tx_clk.

A technology specific clock driver is required to generate a clock centered with the GMII or RGMII data from the MAC. The clock driver can be a PLL, a delay line or a DDR flip-flop.

Figure 18. Gigabit PHY to MAC via GMII

Programmable 10/100/1000 Ethernet Operation

Connect 10/100 Ethernet PHYs to the MAC function via MII. On the receive path, connect the 25-MHz (100 Mbps) or 2.5-MHz (10 Mbps) clock provided by the PHY device to the MAC clock, rx_clk. On the transmit path, connect the 25 MHz (100 Mbps) or a 2.5 MHz (10 Mbps) clock provided by the PHY to the MAC clock, tx_clk.

Figure 19. 10/100 PHY Interface

Programmable 10/100 Ethernet

Typically, 10/100/1000 Ethernet PHY devices implement a shared interface that you connect to a 10/100-Mbps MAC via MII/RGMII or to a gigabit MAC via GMII/RGMII.

On the receive path, connect the clock provided by the PHY device (2.5 MHz, 25 MHz or 125 MHz) to the MAC clock, rx_clk. The PHY interface is connected to both the MII (active PHY signals) and GMII of the MAC function.

On the transmit path, standard programmable PHY devices operating in 10/100 mode generate a 2.5 MHz (10 Mbps) or a 25 MHz (100 Mbps) clock. In gigabit mode, the PHY device expects a 125-MHz clock from the MAC function. Because the MAC function does not generate a clock output, an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices. In 10/100 mode, the clock generated by the MAC to the PHY can be tri-stated.

During transmission, the MAC control signal eth_mode selects either MII or GMII. The MAC function asserts the eth_mode signal when the MAC function operates in gigabit mode, which subsequently drives the MAC GMII to the PHY interface. The eth_mode signal is deasserted when the MAC function operates in 10/100 mode. In this mode, the MAC MII is driven to the PHY interface.

Figure 20. 10/100/1000 PHY Interface via MII/GMII

Figure 21. 10/100/1000 PHY Interface via RGMII

1000BASE-X/SGMII PCS With Optional Embedded PMA

The Intel FPGA 1000BASE-X/SGMII PCS function implements the functionality specified by IEEE 802.3 Clause 36. The PCS function is accessible via MII (SGMII) or GMII (1000BASE-X/SGMII). The PCS function interfaces to an on- or off-chip SERDES component via the industry standard ten-bit interface (TBI).

You can configure the PCS function to include an embedded physical medium attachment (PMA) with a a serial transceiver or LVDS I/O and soft CDR. The PMA interoperates with an external physical medium dependent (PMD) device, which drives the external copper or fiber network. The interconnect between Intel FPGA and PMD devices can be TBI or 1.25 Gbps serial.

The PCS function supports the following external PHYs:

1000 BASE-X PHYs as is.
10BASE-T, 100BASE-T and 1000BASE-T PHYs if the PHYs support SGMII.

1000BASE-X/SGMII PCS Architecture

Figure 22. 1000BASE-X/SGMII PCS

Figure 23. 1000BASE-X/SGMII PCS with Embedded PMA

Transmit Operation

The transmit operation includes frame encapsulation and encoding.

Frame Encapsulation

The PCS function replaces the first preamble byte in the MAC frame with the start of frame /S/ symbol. Then, the PCS function encodes the rest of the bytes in the MAC frame with standard 8B/10B encoded characters. After the last FCS byte, the PCS function inserts the end of frame sequence, /T/ /R/ /R/ or /T/ /R/, depending on the number of character transmitted. Between frames, the PCS function transmits /I/ symbols.

If the PCS function receives a frame from the MAC function with an error (gm_tx_err asserted during frame transmission), the PCS function encodes the error by inserting a /V/ character.

8b/10b Encoding

The 8B/10B encoder maps 8-bit words to 10-bit symbols to generate a DC balance and ensure disparity of the stream with a maximum run length of 5.

Receive Operation

The receive operation includes comma detection, decoding, de-encapsulation, synchronization, and carrier sense.

Comma Detection

The comma detection function searches for the 10-bit encoded comma character, K28.1/K28.5/K28.7, in consecutive samples received from PMA devices. When the K28.1/K28.5/K28.7 comma code group is detected, the PCS function realigns the data stream on a valid 10-bit character boundary. A standard 8b/10b decoder can subsequently decodes the aligned stream.

The comma detection function restarts the search for a valid comma character if the receive synchronization state machine loses the link synchronization.

8b/10b Decoding

The 8b/10b decoder performs the disparity checking to ensure DC balancing and produces a decoded 8-bit stream of data for the frame de-encapsulation function.

Frame De-encapsulation

The frame de-encapsulation state machine detects the start of frame when the /I/ /S/ sequence is received and replaces the /S/ with a preamble byte (0x55). It continues decoding the frame bytes and transmits them to the MAC function. The /T/ /R/ /R/ or the /T/ /R/ sequence is decoded as an end of frame.

A /V/ character is decoded and sent to the MAC function as frame error. The state machine decodes sequences other than /I/ /I/ (Idle) or /I/ /S/ (Start of Frame) as wrong carrier.

During frame reception, the de-encapsulation state machine checks for invalid characters. When the state machine detects invalid characters, it indicates an error to the MAC function.

Synchronization

The link synchronization constantly monitors the decoded data stream and determines if the underlying receive channel is ready for operation. The link synchronization state machine acquires link synchronization if the state machine receives three code groups with comma consecutively without error.

When link synchronization is acquired, the link synchronization state machine counts the number of invalid characters received. The state machine increments an internal error counter for each invalid character received and incorrectly positioned comma character. The internal error counter is decremented when four consecutive valid characters are received. When the counter reaches 4, the link synchronization is lost.

The PCS function drives the led_link signal to 1 when link synchronization is acquired. This signal can be used as a common visual activity check using a board LED.

The PCS function drives the led_panel_link signal to 1 when link synchronization is acquired for the PCS operating in 1000 Base-X without auto negotiation and SGMII mode without auto negotiation.

Carrier Sense

The carrier sense state machine detects an activity when the link synchronization is acquired and when the transmit and receive encapsulation or de-encapsulation state machines are not in the idle or error states.

The carrier sense state machine drives the mii_rx_crs and led_crs signals to 1 when it detects an activity. The led_crs signal can be used as a common visual activity check using a board LED.

Collision Detection

A collision happens when non-idle frames are received from the PHY and transmitted to the PHY simultaneously. Collisions can be detected only in SGMII and half-duplex mode.

When a collision happens, the collision detection state machine drives the mii_rx_col and led_col signals to 1. You can use the led_col signal as a visual check using a board LED.

Transmit and Receive Latencies

Intel uses the following definitions for the transmit and receive latencies for the PCS function with an embedded PMA:

Transmit latency is the time the PCS function takes to transmit the first bit on the PMA-PCS interface after the bit was first available on the MAC side interface (MII/GMII).
Receive latency is the time the PCS function takes to present the first bit on the MAC side interface (MII/GMII) after the bit was received on the PMA-PCS interface.

Table 32. PCS Transmit and Receive Latency.
For GXB, the TX latencies are obtained from sim:/tb/dut/gmii_tx_d or sim:/tb/dut/mii_tx_d (after `clkena` is asserted) to sim:/tb/dut/i_tse_pcs_0/tx_frame. The RX latencies are obtained from sim:/tb/dut/gmii_rx_d or sim:/tb/dut/mii_rx_d to sim:/tb/dut/i_tse_pcs_0/tx_frame.

For LVDS, the TX latencies are obtained from the TX latencies are obtained from sim:/tb/dut/gmii_tx_d or sim:/tb/dut/mii_tx_d (after `clkena` is asserted) to sim:/tb/dut/i_tse_pcs_0/tbi_tx_d_muxed. The RX latencies are obtained from sim:/tb/dut/gmii_rx_d or sim:/tb/dut/mii_rx_d to sim:/tb/dut/i_tse_pcs_0/tbi_rx_d_lvds.
PCS Configuration	Latency (ns)
PCS Configuration	Transmit	Receive
Stratix^® IV
10-Mbps SGMII PCS with GXB	3456	1454.85
100-Mbps SGMII PCS with GXB	376	214.8
1000-Mbps SGMII PCS with GXB	104	142.8
1000BASE-X with GXB	8	48
10-Mbps SGMII PCS with LVDS I/O	3064	1720
100-Mbps SGMII PCS with LVDS I/O	384	280
1000-Mbps SGMII PCS with LVDS I/O	136	192
1000BASE-X PCS with LVDS I/O	40	96
Intel^® Arria^® 10
10-Mbps SGMII PCS with GXB	3600	1867.65
100-Mbps SGMII PCS with GXB	360	187.65
1000-Mbps SGMII PCS with GXB	104	139.65
1000BASE-X with GXB	8	48
10-Mbps SGMII PCS with LVDS I/O	3208	1176
100-Mbps SGMII PCS with LVDS I/O	368	256
1000-Mbps SGMII PCS with LVDS I/O	136	192
1000BASE-X PCS with LVDS I/O	40	96
Intel^® Cyclone^® 10 GX
10-Mbps SGMII PCS with GXB	3600	1867.65
100-Mbps SGMII PCS with GXB	360	187.65
1000-Mbps SGMII PCS with GXB	104	139.65
1000BASE-X with GXB	8	48
10-Mbps SGMII PCS with LVDS I/O	3208	1176
100-Mbps SGMII PCS with LVDS I/O	368	256
1000-Mbps SGMII PCS with LVDS I/O	136	192
1000BASE-X PCS with LVDS I/O	40	96
Intel^® Stratix^® 10
10-Mbps SGMII PCS with LVDS I/O	3336	1840
100-Mbps SGMII PCS with LVDS I/O	456	280
1000-Mbps SGMII PCS with LVDS I/O	112	208
1000BASE-X PCS with LVDS I/O with no Enable SGMII	40	104

SGMII Converter

You can enable the SGMII converter by setting the SGMII_ENA bit in the if_mode register to 1. When enabled and the USE_SGMII_AN bit in the if_mode register is set to 1, the SGMII converter is automatically configured with the capabilities advertised by the PHY. Otherwise, Intel recommends that you configure the SGMII converter with the SGMII_SPEED bits in the if_mode register.

In 1000BASE-X mode, the PCS function always operates in gigabit mode and data duplication is disabled.

Transmit

In gigabit mode, the PCS and MAC functions must operate at the same rate. The transmit converter transmits each byte from the MAC function once to the PCS function.

In 100-Mbps mode, the transmit converter replicates each byte received by the PCS function 10 times. In 10 Mbps, the transmit converter replicates each byte transmitted from the MAC function to the PCS function 100 times.

Receive

In gigabit mode, the PCS and MAC functions must operate at the same rate. The transmit converter transmits each byte from the PCS function once to the MAC function.

In 100-Mbps mode, the receive converter transmits one byte out of 10 bytes received from the PCS function to the MAC function. In 10-Mbps, the receive converter transmits one byte out of 100 bytes received from the PCS function to the MAC function.

Auto-Negotiation

Auto-negotiation is an optional function that can be started when link synchronization is acquired during system start up. To start auto-negotiation automatically, set the AUTO_NEGOTIATION_ENABLE bit in the PCS control register to 1. During auto-negotiation, the PCS function advertises its device features and exchanges them with a link partner device.

If the SGMII_ENA bit in the if_mode register is set to 0, the PCS function operates in 1000BASE-X. Otherwise, the operating mode is SGMII. The following sections describe the auto-negotiation process for each operating mode.

When simulating your design, you can disable auto-negotiation to reduce the simulation time. If you enable auto-negotiation in your design, set the link_timer time to a smaller value to reduce the auto-negotiation link timer in the simulation.

1000BASE-X Auto-Negotiation

When link synchronization is acquired, the PCS function starts sending a /C/ sequence (configuration sequence) to the link partner device with the advertised register set to 0x00. The sequence is sent for a time specified in the PCS link_timer register mapped in the PCS register space.

When the link_timer time expires, the PCS dev_ability register is advertised, with the ACK bit set to 0 for the link partner. The auto-negotiation state machine checks for three consecutive /C/ sequences received from the link partner.

The auto-negotiation state machine then sets the ACK bit to 1 in the advertised dev_ability register and checks if three consecutive /C/ sequences are received from the link partner with the ACK bit set to 1.

Auto-negotiation waits for the value configured in the link_timer register to ensure no more consecutive /C/sequences are received from the link partner. The auto-negotiation is successfully completed when three consecutive idle sequences are received after the link timer expires.

After auto-negotiation completes successfully, the user software reads both the dev_ability and partner_ability register and proceed to resolve priority for duplex mode and pause mode. If the design contains a MAC and PCS, the user software configures the MAC with a proper resolved pause mode by setting the PAUSE_IGNORE bit in command_config register. To disable pause frame generation based on the receive FIFO buffer level, you should set the rx_section_empty register accordingly.

Figure 24. Auto-Negotiation Activity (Simplified)

Once auto-negotiation completes successfully, the ability advertised by the link partner device is available in the partner_ability register and the AUTO_NEGOTIATION_COMPLETE bit in the status register is set to 1.

The PCS function restarts auto-negotiation when link synchronization is lost and reacquired, or when you set the RESTART_AUTO_NEGOTIATION bit in the PCS control register to 1.

SGMII Auto-Negotiation

In SGMII mode, the capabilities of the PHY device are advertised and exchanged with a link partner PHY device.

Possible application of SGMII auto-negotiation in MAC mode and PHY mode.

Figure 25. SGMII Auto-Negotiation in MAC Mode and PHY Mode

If the SGMII_ENA and USE_SGMII_AN bits in the if_mode register are 1, the PCS function is automatically configured with the capabilities advertised by the PHY device once the auto-negotiation completes.

If the SGMII_ENA bit is 1 and the USE_SGMII_AN bit is 0, the PCS function can be configured with the SGMII_SPEED and SGMII_DUPLEX bits in the if_mode register.

If the SGMII_ENA bit is 1 and the SGMII_AN_MODE bit is 1 (SGMII PHY Mode auto-negotiation is enabled) the speed and duplex mode resolution will be resolved based on the value that you set in the dev_ability register once auto negotiation is done. You should use set to the PHY mode if you want to advertise the link speed and duplex mode to the link partner.

Figure 26. SGMII Auto-Negotiation Activity

For more information, refer to CISCO Serial-GMII Specifications.

PHY Loopback

In PCS variations with embedded PMA, the PCS function implements a TBI to an external SERDES.

On transmit, the SERDES must serialize tbi_tx_d[0], the least significant bit of the TBI output bus first and tbi_tx_d[9], the most significant bit of the TBI output bus last to ensure the remote node receives the data correctly, as figure below illustrates.

Figure 27. SERDES Serialization Overview

On receive, the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last, as figure below illustrates.

Figure 28. SERDES De-Serialization Overview

PHY Loopback

In PCS variations with embedded PMA targeting devices with GX transceivers, you can enable loopback on the serial interface to test the PCS and embedded PMA functions in isolation of the PMD. To enable loopback, set the sd_loopback bit in the PCS control register to 1.

The serial loopback option is not supported in Cyclone^® IV devices with GX transceiver.

Figure 29. Serial Loopback

PHY Power-Down

Power-down is controlled by the POWERDOWN bit in the PCS control register. When the system management agent enables power-down, the PCS function drives the powerdown signal, which can be used to control a technology specific circuit to switch off the PCS function clocks to reduce the application activity.

When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmit and the TBI receive interfaces are ignored. The management interface remains active and responds to management transactions from the MAC layer device.

Figure 30. Power-Down

Power-Down in PCS Variations with Embedded PMA

In PCS variations with embedded PMA targeting devices with GX transceivers, the power-down signal is internally connected to the power-down of the GX transceiver. In these devices, the power-down functionality is shared across quad-port transceiver blocks. Ethernet designs must share a common gbx_pwrdn_in signal to use the same quad-port transceiver block.

For designs targeting devices other than Stratix V, you can export the power-down signals to implement your own power-down logic to efficiently use the transceivers within a particular transceiver quad. Turn on the Export transceiver powerdown signal parameter to export the signals.

Figure 31. Power-Down with Export Transceiver Power-Down Signal

Reset

A hardware reset resets all logic synchronized to the respective clock domains whereas a software reset only resets the PCS state machines, comma detection function, and 8B10B encoder and decoder. To trigger a hardware reset on the PCS, assert the respective reset signals: reset_reg_clk, reset_tx_clk, and reset_rx_clk. To trigger a software reset, set the RESET bit in the control register to 1.

In PCS variations with embedded PMA, assert the respective reset signals or the power-down signal to trigger a hardware reset. You must assert the reset signal subsequent to asserting the reset_rx_clk, reset_tx_clk, or gbx_pwrdn_in signal. The reset sequence is also initiated when the active-low rx_freqlocked signal goes low.

Figure 32. Reset Distribution in PCS with Embedded PMA

For more information about the rx_freqlocked signal and transceiver reset, refer to the transceiver handbook of the respective device family.

Assert the reset or gxb_pwrdn_in signals to perform a hardware reset on MAC with PCS and embedded PMA variation.

Note: You must assert the reset signal for at least three clock cycles.

Figure 33. Reset Distribution in MAC with PCS and Embedded PMA

Intel FPGA IEEE 1588v2 Feature

The Intel FPGA IEEE 1588v2 feature provides timestamp for receive and transmit frames in the Triple-Speed Ethernet IP core designs. The feature consists of Precision Time Protocol (PTP). PTP is a layer-3 protocol that accurately synchronizes all real time-of-day clocks in a network to a master clock.

This feature is supported in Arria^® V, Intel^® Arria^® 10, Cyclone^® V, Intel^® Cyclone^® 10 GX, Intel^® MAX^® 10, Stratix^® V, and Intel^® Stratix^® 10 device families.

IEEE 1588v2 Supported Configurations

The Triple-Speed Ethernet IP core supports the IEEE 1588v2 feature only in the following configurations:

10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded serial PMA without FIFO buffer in full-duplex mode
10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded LVDS I/O without FIFO buffer in full-duplex mode
10/100/1000-Mbps MAC without FIFO buffer in full-duplex mode

IEEE 1588v2 Features

Supports 4 types of PTP clock on the transmit datapath:
- Master and slave ordinary clock
- Master and slave boundary clock
- End-to-end (E2E) transparent clock
- Peer-to-peer (P2P) transparent clock
Supports PTP message types:
- PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
- PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce, Management, and Signaling.
Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath.
- 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message or updates the correction field with residence time.
- 2-step clock synchronization—The MAC function provides accurate timestamp and the related fingerprint for all PTP message.
Supports the following PHY operating speed accuracy:
- random error:
  - 10Mbps—NA
  - 100Mbps—timestamp accuracy of ± 5 ns
  - 1000Mbps—timestamp accuracy of ± 2 ns
- static error—timestamp accuracy of ± 3 ns
Supports IEEE 802.3, UDP/IPv4, and UDP/IPv6 transfer protocols for the PTP frames.
Supports untagged, VLAN tagged, Stacked VLAN Tagged PTP frames, and any number of MPLS labels.
Supports configurable register for timestamp correction on both transmit and receive datapaths.
Supports Time-of-Day (ToD) clock that provides a stream of 64-bit and 96-bit timestamps.

Architecture

Figure 34. Overview of the IEEE 1588v2 Feature. This figure shows only the datapaths related to the IEEE 1588v2 feature.

Transmit Datapath

The IEEE 1588v2 feature supports 1-step and 2-step clock synchronizations on the transmit datapath.

For 1-step clock synchronization:
- Timestamp insertion depends on the PTP device and message type.
- The MAC function inserts a timestamp in the Sync PTP message if the PTP clock operates as ordinary or boundary clock.
- Depending on the PTP device and message type, the MAC function updates the residence time in the correction field of the PTP frame when the client asserts tx_etstamp_ins_ctrl_residence_time_update. The residence time is the difference between the egress and ingress timestamps.
- For PTP frames encapsulated using the UDP/IPv6 protocol, the MAC function performs UDP checksum correction using extended bytes in the PTP frame.
- The MAC function re-computes and re-inserts CRC-32 into the PTP frames after each timestamp or correction field insertion.
For 2-step clock synchronization, the MAC function returns the timestamp and the associated fingerprint for all transmit frames when the client asserts tx_egress_timestamp_request_valid.

Table 33. Timestamp and Correction Insertion for 1-Step Clock Synchronization. This table summarizes the timestamp and correction field insertions for various PTP messages in different PTP clocks.
PTP Message	Ordinary Clock		Boundary Clock		E2E Transparent Clock		P2P Transparent Clock
PTP Message	Insert Time stamp	Insert Correction	Insert Time stamp	Insert Correction	Insert Time stamp	Insert Correction	Insert Time stamp	Insert Correction
Sync	Yes (1)	No	Yes (1)	No	No	Yes (2)	No	Yes (2)
Delay_Req	No	No	No	No	No	Yes (2)	No	Yes (2)
Pdelay_Req	No	No	No	No	No	Yes (2)	No	No
Pdelay_Resp	No	Yes (1), (2)	No	Yes (1), (2)	No	Yes (2)	No	Yes (1), (2)
Delay_Resp	No	No	No	No	No	No	No	No
Follow_Up	No	No	No	No	No	No	No	No
Pdelay_Resp_Follow_Up	No	No	No	No	No	No	No	No
Announce	No	No	No	No	No	No	No	No
Signaling	No	No	No	No	No	No	No	No
Management	No	No	No	No	No	No	No	No
Notes to Table 1 : Applicable only when 2-step flag in `flagField` of the PTP frame is 0. Applicable when you assert `tx_ingress_timestamp_request_valid`.

Receive Datapath

In the receive datapath, the IEEE 1588v2 feature provides a timestamp for all receive frames. The timestamp is aligned with the avalon_st_rx_startofpacket signal.

Frame Format

The MAC function, with the IEEE 1588v2 feature, supports PTP frame transfer for the following transport protocols:

IEEE 802.3
UDP/IPv4
UDP/IPv6

PTP Frame in IEEE 802.3

Figure 35. PTP Frame in IEEE 8002.3

Note to Figure 1 :

For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

PTP Frame over UDP/IPv4

Checksum calculation is optional for the UDP/IPv4 protocol. The 1588v2 Tx logic should set the checksum to zero.

Figure 36. PTP Frame over UDP/IPv4

Note to Figure 1 :

For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

PTP Frame over UDP/IPv6

Checksum calculation is mandatory for the UDP/IPv6 protocol. You must extend 2 bytes at the end of the UDP payload of the PTP frame. The MAC function modifies the extended bytes to ensure that the UDP checksum remains uncompromised.

Figure 37. PTP Frame over UDP/IPv6

Note to Figure 1 :

For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

Configuration Register Space

MAC Configuration Register Space

Use the registers to configure the different aspects of the MAC function and retrieve its status and statistics counters.

In multiport MACs, a contiguous register space is allocated for all ports and accessed via the Avalon-MM control interface. For example, if the register space base address for the first port is 0x00, the base address for the next port is 0x100 and so forth. The registers that are shared among the instances occupy the register space of the first port. Updating these registers in the register space of other ports has no effect on the configuration.

Table 34. Overview of MAC Register Space
Dword Offset	Section	Description
0x00 – 0x17	Base Configuration	Base registers to configure the MAC function. At the minimum, you must configure the following functions: Primary MAC address (`mac_0`/`mac_1`) Enable transmit and receive paths (`TX_ENA` and `RX_ENA` bits in the `command_config` register) The following registers are shared among all instances of a multiport MAC: `rev` `scratch` `frm_length` `pause_quant` `mdio_addr0` and `mdio_addr1` `tx_ipg_length` For more information about the base configuration registers, refer to Base Configuration Registers (Dword Offset 0x00 – 0x17).
0x18 – 0x38	Statistics Counters	Counters collecting traffic statistics. For more information about the statistics counters, refer to Statistics Counters (Dword Offset 0x18 – 0x38).
0x3A	Transmit Command	Transmit and receive datapaths control register. For more information about these registers, see Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B).
0x3B	Receive Command
0x3C – 0x3E	Extended Statistics Counters	Upper 32 bits of selected statistics counters. These registers are used if you turn on the option to use extended statistics counters. For more information about these counters, refer to Statistics Counters (Dword Offset 0x18 – 0x38) .
0x3F	Reserved	Unused.
0x40 – 0x7F	Multicast Hash Table	64-entry write-only hash table to resolve multicast addresses. Only bit 0 in each entry is significant. When you write a 1 to a dword offset in the hash table, the MAC accepts all multicast MAC addresses that hash to the value of the address (bits 5:0). Otherwise, the MAC rejects the multicast address. This table is cleared during reset. Hashing is not supported in 10/100 and 1000 Mbps Small MAC core variations.
0x80 – 0x9F	MDIO Space 0 or PCS Function Configuration	MDIO Space 0 and MDIO Space 1 map to registers 0 to 31 of the PHY devices whose addresses are configured in the `mdio_addr0` and `mdio_addr1` registers respectively. For example, register 0 of PHY device 0 maps to dword offset 0x80, register 1 maps to dword offset 0x81 and so forth. Reading or writing to MDIO Space 0 or MDIO Space 1 immediately triggers a corresponding MDIO transaction to read or write the PHY register. Only bits [15:0] of each register are significant. Write 0 to bits [31:16] and ignore them on reads. If your variation does not include the PCS function, you can use MDIO Space 0 and MDIO Space 1 to map to two PHY devices. If your MAC variation includes the PCS function, the PCS function is always device 0 and its configuration registers (PCS Configuration Register Space) occupy MDIO Space 0. You can use MDIO Space 1 to map to a PHY device.
0xA0 – 0xBF	MDIO Space 1
0xC0 – 0xC7	Supplementary Address	Supplementary unicast addresses. For more information about these addresses, refer to Supplementary Address (Dword Offset 0xC0 – 0xC7).
0xC8 – 0xCF	Reserved (1)	Unused.
0xD0 – 0xD6	IEEE 1588v2 Feature	Registers to configure the IEEE 1588v2 feature. For more information about these registers, refer to IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6).
0xD7 – 0xFF	Reserved (1)	Unused.
Note to Table 1: Intel recommends that you set all bits in the reserved registers to 0 and ignore them on reads.

Base Configuration Registers (Dword Offset 0x00 – 0x17)

The following table lists the base registers you can use to configure the MAC function. A software reset does not reset these registers except the first two bits (TX_ENA and RX_ENA = 0) in the command_config register.

Table 35. Base Configuration Register Map
Dword Offset	Name	R/W	Description	HW Reset
0x00	`rev`	RO	Bits[15:0]—Set to the current version of the IP core. Bits[31:16]—Customer specific revision, specified by the `CUST_VERSION` parameter defined in the top-level file generated for the instance of the IP core. These bits are set to 0 during the configuration of the IP core.	<IP version number>
0x01	`scratch` (1)	RW	Scratch register. Provides a memory location for you to test the device memory operation.	0
0x02	`command_config`	RW	MAC configuration register. Use this register to control and configure the MAC function. The MAC function starts operation as soon as the transmit and receive enable bits in this register are turned on. Intel, therefore, recommends that you configure this register last. See Command_Config Register (Dword Offset 0x02) for the bit description.	0
0x03	`mac_0`	RW	6-byte MAC primary address. The first four most significant bytes of the MAC address occupy `mac_0` in reverse order. The last two bytes of the MAC address occupy the two least significant bytes of `mac_1` in reverse order. For example, if the MAC address is 00-1C-23-17-4A-CB, the following assignments are made: `mac_0` = 0x17231c00 `mac_1` = 0x0000CB4a Ensure that you configure these registers with a valid MAC address if you disable the promiscuous mode (`PROMIS_EN` bit in `command_config` = 0).	0
0x04	`mac_1`	RW		0
0x05	`frm_length`	RW/ RO	Bits[15:0]—16-bit maximum frame length in bytes. The IP core checks the length of receive frames against this value. Typical value is 1518. In 10/100 and 1000 Small MAC core variations, this register is RO and the maximum frame length is fixed to 1518. Bits[31:16]—unused.	1518
0x06	`pause_quant`	RW	Bits[15:0]—16-bit pause quanta. Use this register to specify the pause quanta to be sent to remote devices when the local device is congested. The IP core sets the pause quanta (P1, P2) field in pause frames to the value of this register. 10/100 and 1000 Small MAC core variations do not support flow control. Bits[31:16]—unused.	0
0x07	`rx_section_empty`	RW/ RO	Variable-length section-empty threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set to (FIFO Depth – 16). Set this threshold to a value that is below the `rx_almost_full` threshold and above the `rx_section_full` or `rx_almost_empty` threshold. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16).	0
0x08	`rx_section_full`	RW/ RO	Variable-length section-full threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. For cut-through mode, this threshold is typically set to 16. Set this threshold to a value that is above the `rx_almost_empty` threshold. For store-and-forward mode, set this threshold to 0. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 16.	0
0x09	`tx_section_empty`	RW/ RO	Variable-length section-empty threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set to (FIFO Depth – 16). Set this threshold to a value below the `rx_almost_full` threshold and above the `rx_section_full` or `rx_almost_empty` threshold. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of (FIFO Depth – 16).	0
0x0A	`tx_section_full`	RW/ RO	Variable-length section-full threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. For cut-through mode, this threshold is typically set to 16. Set this threshold to a value above the `tx_almost_empty` threshold. For store-and-forward mode, set this threshold to 0. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 16.	0
0x0B	`rx_almost_empty`	RW/ RO	Variable-length almost-empty threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.	0
0x0C	`rx_almost_full`	RW/ RO	Variable-length almost-full threshold of the receive FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.	0
0x0D	`tx_almost_empty`	RW/ RO	Variable-length almost-empty threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.	0
0x0E	`tx_almost_full`	RW/ RO	Variable-length almost-full threshold of the transmit FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. You must set this register to a value greater than or equal to 3. A value of 3 indicates 0 ready latency; a value of 4 indicates 1 ready latency, and so forth. Because the maximum ready latency on the Avalon-ST interface is 8, you can only set this register to a maximum value of 11. This threshold is typically set to 3. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 3.	0
0x0F	`mdio_addr0`	RW	Bits[4:0]—5-bit PHY address. Set these registers to the addresses of any connected PHY devices you want to access. The `mdio_addr0` and `mdio_addr1` registers contain the addresses of the PHY whose registers are mapped to MDIO Space 0 and MDIO Space 1 respectively. Bits[31:5]—unused. Set to read-only value of 0.	0
0x10	`mdio_addr1`	RW		1
0x11	`holdoff_quant`	RW	Bit[15:0]—16-bit holdoff quanta. When you enable the flow control, use this register to specify the gap between consecutive XOFF requests. Bits[31:16]—unused.	0xFFFF
0x12 – 0x16	Reserved	—	—	0
0x17	`tx_ipg_length`	RW	Bits[4:0]—minimum IPG. Valid values are between 8 and 26 byte-times. If this register is set to an invalid value, the MAC still maintains a typical minimum IPG value of 12 bytes between packets, although a read back to the register reflects the invalid value written. In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 12. Bits[31:5]—unused. Set to read-only value 0.	0
Note to Table 1 : Register is not available in 10/100 and 1000 Small MAC variations.

Command_Config Register (Dword Offset 0x02)

Figure 38. Command_Config Register Fields

At the minimum, you must configure the TX_ENA and RX_ENA bits to 1 to start the MAC operations. When configuring the command_config register, Intel^® recommends that you configure the TX_ENA and RX_ENA bits the last because the MAC function immediately starts its operations once these bits are set to 1.

Table 36. Command_Config Register Field Descriptions
Bit(s)	Name	R/W	Description
0	`TX_ENA`	RW	Transmit enable. Set this bit to 1 to enable the transmit datapath. The MAC function clears this bit following a hardware or software reset. See the `SW_RESET` bit description.
1	`RX_ENA`	RW	Receive enable. Set this bit to 1 to enable the receive datapath. The MAC function clears this bit following a hardware or software reset. See the `SW_RESET` bit description.
2	`XON_GEN`	RW	Pause frame generation. When you set this bit to 1, the MAC function generates a pause frame with a pause quanta of 0, independent of the status of the receive FIFO buffer.
3	`ETH_SPEED`	RW	Ethernet speed control. Set this bit to 1 to enable gigabit Ethernet operation. The `set_1000` signal is masked and does not affect the operation. If you set this bit to 0, gigabit Ethernet operation is enabled only if the `set_1000` signal is asserted. Otherwise, the MAC function operates in 10/100 Mbps Ethernet mode. When the MAC operates in gigabit mode, the `eth_mode` signal is asserted. This bit is not available in the small MAC variation.
4	`PROMIS_EN`	RW	Promiscuous enable. Set this bit to 1 to enable promiscuous mode. In this mode, the MAC function receives all frames without address filtering.
5	`PAD_EN`	RW	Padding removal on receive. Set this bit to 1 to remove padding from receive frames before the MAC function forwards the frames to the user application. This bit has no effect on transmit frames. This bit is not available in the small MAC variation.
6	`CRC_FWD`	RW	CRC forwarding on receive. Set this bit to 1 to forward the CRC field to the user application. Set this bit to 0 to remove the CRC field from receive frames before the MAC function forwards the frame to the user application. The MAC function ignores this bit when it receives a padded frame and the `PAD_EN`bit is 1. In this case, the MAC function checks the CRC field and removes the checksum and padding from the frame before forwarding the frame to the user application.
7	`PAUSE_FWD`	RW	Pause frame forwarding on receive. Set this bit to 1 to forward receive pause frames to the user application. Set this bit to 0 to terminate and discard receive pause frames.
8	`PAUSE_IGNORE`	RW	Pause frame processing on receive. Set this bit to 1 to ignore receive pause frames. Set this bit to 0 to process receive pause frames. The MAC function suspends transmission for an amount of time specified by the pause quanta.
9	`TX_ADDR_INS`	RW	MAC address on transmit. Set this bit to 1 to overwrite the source MAC address in transmit frames received from the user application with the MAC primary or supplementary address configured in the registers. The `TX_ADDR_SEL` bit determines the address selection. Set this bit to 0 to retain the source MAC address in transmit frames received from the user application.
10	`HD_ENA`	RW	Half-duplex enable. Set this bit to 1 to enable half-duplex. Set this bit to 0 to enable full-duplex. The MAC function ignores this bit if you set the `ETH_SPEED` bit to 1.
11	`EXCESS_COL`	RO	Excessive collision condition. The MAC function sets this bit to 1 when it discards a frame after detecting a collision on 16 consecutive frame retransmissions. The MAC function clears this bit following a hardware or software reset. See the `SW_RESET` bit description.
12	`LATE_COL`	RO	Late collision condition. The MAC function sets this bit to 1 when it detects a collision after transmitting 64 bytes and discards the frame. The MAC function clears this bit following a hardware or software reset. See the `SW_RESET` bit description.
13	`SW_RESET`	RW	Software reset. Set this bit to 1 to trigger a software reset. The MAC function clears this bit when it completes the software reset sequence. When software reset is triggered, the MAC function completes the current transmission or reception, and subsequently disables the transmit and receive logic, flushes the receive FIFO buffer, and resets the statistics counters.
14	`MHASH_SEL`	RW	Hash-code mode selection for multicast address resolution. Set this bit to 0 to generate the hash code from the full 48-bit destination address. Set this bit to 1 to generate the hash code from the lower 24 bits of the destination MAC address.
15	`LOOP_ENA`	RW	Local loopback enable. Set this bit to 1 to enable local loopback on the RGMII/GMII/MII of the MAC. The MAC function sends transmit frames back to the receive path. This bit is not available in the small MAC variation.
18 – 16	`TX_ADDR_SEL`[2:0]	RW	Source MAC address selection on transmit. If you set the `TX_ADDR_INS` bit to 1, the value of these bits determines the MAC address the MAC function selects to overwrite the source MAC address in frames received from the user application. 000 = primary address configured in the `mac_0`and `mac_1` registers. 100 = supplementary address configured in the `smac_0_0` and `smac_0_1` registers. 101 = supplementary address configured in the `smac_1_0` and `smac_1_1` registers. 110 = supplementary address configured in the `smac_2_0` and `smac_2_1`registers. 111 = supplementary address configured in the `smac_3_0`and `smac_3_1`registers.
19	`MAGIC_ENA`	RW	Magic packet detection. Set this bit to 1 to enable magic packet detection. This bit is not available in the small MAC variation.
20	`SLEEP`	RW	Sleep mode enable. When the `MAGIC_ENA` bit is 1, set this bit to 1 to put the MAC function to sleep and enable magic packet detection. This bit is not available in the small MAC variation.
21	`WAKEUP`	RO	Node wake-up request. Valid only when the `MAGIC_ENA` bit is 1. The MAC function sets this bit to 1 when a magic packet is detected. The MAC function clears this bit when the `SLEEP` bit is set to 0.
22	`XOFF_GEN`	RW	Pause frame generation. Set this bit to 1 to generate a pause frame independent of the status of the receive FIFO buffer. The MAC function sets the pause quanta field in the pause frame to the value configured in the `pause_quant` register.
23	`CNTL_FRM_ENA`	RW	MAC control frame enable on receive. Set this bit to 1 to accept control frames other than pause frames (opcode = 0x0001) and forward them to the user application. Set this bit to 0 to discard control frames other than pause frames.
24	`NO_LGTH_CHECK`	RW	Payload length check on receive. Set this bit to 0 to check the actual payload length of receive frames against the length/type field in receive frames. Set this bit to 1 to omit length checking. This bit is not available in the small MAC variation
25	`ENA_10`	RW	10-Mbps interface enable. Set this bit to 1 to enable the 10-Mbps interface. The MAC function asserts the `ena_10` signal when you enable the 10-Mbps interface. You can also enable the 10-Mbps interface by asserting the `set_10` signal.
26	`RX_ERR_DISC`	RW	Erroneous frames processing on receive. Set this bit to 1 to discard erroneous frames received. This applies only when you enable store and forward operation in the receive FIFO buffer by setting the `rx_section_full` register to 0. Set this bit to 0 to forward erroneous frames to the user application with `rx_err[0]` asserted.
27	`DISABLE_READ_TIMEOUT`	RW	By default, this bit is set to 0. Set this bit to 1 to disable MAC configuration register read timeout. To ensure the configuration register does not wait for read timeout when an error occurs, set this bit to 1.
28 – 30	Reserved	—	—
31	`CNT_RESET`	RW	Statistics counters reset. Set this bit to 1 to clear the statistics counters. The MAC function clears this bit when the reset sequence completes.

Statistics Counters (Dword Offset 0x18 – 0x38)

The following table describes the read-only registers that collect the statistics on the transmit and receive datapaths. A hardware reset clears these registers; a software reset also clears these registers except aMacID. The statistics counters roll up when the counter is full.

The register description uses the following definitions:

Good frame—error-free frames with valid frame length.
Error frame—frames that contain errors or whose length is invalid.
Invalid frame—frames that are not addressed to the MAC function. The MAC function drops this frame.

Table 37. Statistics Counters
Dword Offset	Name	R/W	Description
0x18 – 0x19	`aMacID`	RO	The MAC address. This register is wired to the primary MAC address in the `mac_0` and `mac_1` registers.
0x1A	`aFramesTransmittedOK`	RO	The number of frames that are successfully transmitted including the pause frames.
0x1B	`aFramesReceivedOK`	RO	The number of frames that are successfully received including the pause frames.
0x1C	`aFrameCheck SequenceErrors`	RO	The number of receive frames with CRC error.
0x1D	`aAlignmentErrors`	RO	The number of receive frames with alignment error.
0x1E	`aOctetsTransmittedOK`	RO	The number of data and padding octets that are successfully transmitted. This register contains the lower 32 bits of the `aOctetsTransmittedOK` counter. The upper 32 bits of this statistics counter reside at the dword offset 0x0F.
0x1F	`aOctetsReceivedOK`	RO	The number of data and padding octets that are successfully received. The lower 32 bits of the `aOctetsReceivedOK` counter. The upper 32 bits of this statistics counter reside at the dword offset 0x3D.
0x20	`aTxPAUSEMACCtrlFrames`	RO	The number of pause frames transmitted.
0x21	`aRxPAUSEMACCtrlFrames`	RO	The number received pause frames received.
0x22	`ifInErrors`	RO	The number of errored frames received.
0x23	`ifOutErrors`	RO	The number of transmit frames with one the following errors: FIFO overflow error FIFO underflow error Errors defined by the user application
0x24	`ifInUcastPkts`	RO	The number of valid unicast frames received.
0x25	`ifInMulticastPkts`	RO	The number of valid multicast frames received. The count does not include pause frames.
0x26	`ifInBroadcastPkts`	RO	The number of valid broadcast frames received.
0x27	`ifOutDiscards`	—	This statistics counter is not in use. The MAC function does not discard frames that are written to the FIFO buffer by the user application.
0x28	`ifOutUcastPkts`	RO	The number of valid unicast frames transmitted.
0x29	`ifOutMulticastPkts`	RO	The number of valid multicast frames transmitted, excluding pause frames.
0x2A	`ifOutBroadcastPkts`	RO	The number of valid broadcast frames transmitted.
0x2B	`etherStatsDropEvents`	RO	The number of frames that are dropped due to MAC internal errors when FIFO buffer overflow persists.
0x2C	`etherStatsOctets`	RO	The total number of octets received. This count includes both good and errored frames. This register is the lower 32 bits of `etherStatsOctets`. The upper 32 bits of this statistics counter reside at the dword offset 0x3E.
0x2D	`etherStatsPkts`	RO	The total number of good and errored frames received.
0x2E	`etherStatsUndersizePkts`	RO	The number of frames received with length less than 64 bytes. This count does not include errored frames.
0x2F	`etherStatsOversizePkts`	RO	The number of frames received that are longer than the value configured in the `frm_length` register. This count does not include errored frames.
0x30	`etherStatsPkts64Octets`	RO	The number of 64-byte frames received. This count includes good and errored frames.
0x31	`etherStatsPkts65to127Octets`	RO	The number of received good and errored frames between the length of 65 and 127 bytes.
0x32	`etherStatsPkts128to255Octets`	RO	The number of received good and errored frames between the length of 128 and 255 bytes.
0x33	`etherStatsPkts256to511Octets`	RO	The number of received good and errored frames between the length of 256 and 511 bytes.
0x34	`etherStatsPkts512to1023Octets`	RO	The number of received good and errored frames between the length of 512 and 1023 bytes.
0x35	`etherStatsPkts1024to1518Octets`	RO	The number of received good and errored frames between the length of 1024 and 1518 bytes.
0x36	`etherStatsPkts1519toXOctets`	RO	The number of received good and errored frames between the length of 1519 and the maximum frame length configured in the `frm_length` register.
0x37	`etherStatsJabbers`	RO	Too long frames with CRC error.
0x38	`etherStatsFragments`	RO	Too short frames with CRC error.
0x39	Reserved	—	Unused
Extended Statistics Counters (0x3C – 0x3E)
0x3C	`msb_aOctetsTransmittedOK`	RO	Upper 32 bits of the respective statistics counters. By default all statistics counters are 32 bits wide. These statistics counters can be extended to 64 bits by turning on the Enable 64-bit byte counters parameter. To read the counter, read the lower 32 bits first, then followed by the extended statistic counter bits.
0x3D	`msb_aOctetsReceivedOK`	RO
0x3E	`msb_etherStatsOctets`	RO

Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)

The following table describes the registers that determine how the MAC function processes transmit and receive frames. A software reset does not change the values in these registers.

Table 38. Transmit and Receive Command Registers
Dword Offset	Name	R/W	Description
0x3A	`tx_cmd_stat`	RW	Specifies how the MAC function processes transmit frames. When you turn on the Align packet headers to 32-bit boundaries option, this register resets to 0x00040000 upon a hardware reset. Otherwise, it resets to 0x00. Bits 0 to 16—unused. Bit 17 (`OMIT_CRC`)—Set this bit to 1 to omit CRC calculation and insertion on the transmit path. The user application is therefore responsible for providing the correct data and CRC. This bit, when set to 1, always takes precedence over the `ff_tx_crc_fwd` signal. Bit 18 (`TX_SHIFT16`)—Set this bit to 1 if the frames from the user application are aligned on 32-bit boundary. For more information, refer to IP Payload Re-alignment. This setting applies only when you turn on the Align packet headers to 32-bit boundary option and in MAC variations with 32-bit internal FIFO buffers. Otherwise, reading this bit always return a 0. In MAC variations without internal FIFO buffers, this bit is a read-only bit and takes the value of the Align packet headers to 32-bit boundary option. Bits 19 to 31—unused.
0x3B	`rx_cmd_stat`	RW	Specifies how the MAC function processes receive frames. When you turn on the Align packet headers to 32-bit boundaries option, this register resets to 0x02000000 upon a hardware reset. Otherwise, it resets to 0x00. Bits 0 to 24—unused. Bit 25 (`RX_SHIFT16`)—Set this bit to 1 to instruct the MAC function to align receive frames on 32-bit boundary. For more information on frame alignment, refer to IP Payload Alignment. This setting applies only when you turn on the Align packet headers to 32-bit boundary option and in MAC variations with 32-bit internal FIFO buffers. Otherwise, reading this bit always return a 0. In MAC variations without internal FIFO buffers, this bit is a read-only bit and takes the value of the Align packet headers to 32-bit boundary option. Bits 26 to 31—unused.

Supplementary Address (Dword Offset 0xC0 – 0xC7)

A software reset has no impact on these registers. MAC supplementary addresses are not available in 10/100 and 1000 Small MAC variations.

Table 39. Supplementary Address Registers
Dword Offset	Name	R/W	Description	HW Reset
0xC0	`smac_0_0`	RW	You can specify up to four 6-byte supplementary addresses: smac_0_0/1 smac_1_0/1 smac_2_0/1 smac_3_0/1 Map the supplementary addresses to the respective registers in the same manner as the primary MAC address. Refer to the description of mac_0 and ma`c_1`. The MAC function uses the supplementary addresses for the following operations: to filter unicast frames when the promiscuous mode is disabled (refer to Command_Config Register (Dword Offset 0x02) for the description of the `PROMIS_EN` bit). to replace the source address in transmit frames received from the user application when address insertion is enabled (refer to Command_Config Register (Dword Offset 0x02) for the description of the `TX_ADDR_INS` and `TX_ADDR_SEL` bits). If you do not require the use of supplementary addresses, configure them to the primary address.	0
0xC1	`smac_0_1`
0xC2	`smac_1_0`
0xC3	`smac_1_1`
0xC4	`smac_2_0`
0xC5	`smac_2_1`
0xC6	`smac_3_0`
0xC7	`smac_3_1`

IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)

Table 40. IEEE 1588v2 MAC Registers
Dword Offset	Name	R/W	Description	HW Reset
0xD0	`tx_period`	RW	Clock period for timestamp adjustment on the transmit datapath. The period register is multiplied by the number of stages separating actual timestamp and the GMII bus. Bits 0 to 15: Period in fractional nanoseconds (`TX_PERIOD_FNS`). Bits 16 to 24: Period in nanoseconds (`TX_PERIOD_NS`). Bits 25 to 31: Not used. The default value for the period is 0. For 125-MHz clock, set this register to 8 ns.	0x0
0xD1	`tx_adjust_fns`	RW	Static timing adjustment in fractional nanoseconds for outbound timestamps on the transmit datapath. Bits 0 to 15: Timing adjustment in fractional nanoseconds. Bits 16 to 31: Not used.	0x0
0xD2	`tx_adjust_ns`	RW	Static timing adjustment in nanoseconds for outbound timestamps on the transmit datapath. Bits 0 to 15: Timing adjustment in nanoseconds. Bits 16 to 23: Not used.	0x0
0xD3	`rx_period`	RW	Clock period for timestamp adjustment on the receive datapath. The period register is multiplied by the number of stages separating actual timestamp and the GMII bus. Bits 0 to 15: Period in fractional nanoseconds (`RX_PERIOD_FNS`). Bits 16 to 24: Period in nanoseconds (`RX_PERIOD_NS`). Bits 25 to 31: Not used. The default value for the period is 0. For 125-MHz clock, set this register to 8 ns.	0x0
0xD4	`rx_adjust_fns`	RW	Static timing adjustment in fractional nanoseconds for outbound timestamps on the receive datapath.

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