This application note describes how to implement the Intel® QuickPath Interconnect (QPI) protocol with Altera® transceivers in the Stratix® V devices. Designers can create the QPI interface design using FPGA logic to interface with the transceiver configurations described in this document.
Stratix V Native PHY IP cores provide an easy and efficient method to implement the QPI protocol.
The QPI is a point-to-point connection protocol developed by Intel to replace the front-side-bus (FSB). It was designed to transfer data between the processors and IO hubs. Compared to a parallel bus, the QPI can achieve higher performance.
QPI is a serial bus technology similar to other point-to-point interconnects. All channels work at the differential IO standard. The physical data rates for QPI can be 4.8, 6.4, or 8 Gbps. The channel links can be defined as full-width for 20 channels, and half-width for 10 channels.
QPI has the following special features, which may differ from other serial interface protocols:
- DC Coupling Mode
The transmitter (TX) and receiver (RX) use DC coupling mode. Per the QPI spec, the connected transceiver pair are DC-coupled.
Stratix V devices have been characterized to be fully compatible with DC mode for QPI interfaces. From the transmitter, the output common mode DC voltage can vary between 0.23 to 0.27 V.
- Bonded TX Channels
All the TX channels must be configured in bonded mode to reduce the channel-to-channel skew. For example, full-width link design will bond all 20 TX channels together.
Stratix V devices can support TX channel bonding for QPI with PLL feedback compensation mode.
To bond all channels using the PLL feedback compensation path, the input reference clock frequency used by the TX PLL must be the same as the parallel clock that clocks the PCS of the same channel. For example, the reference clock is 250 MHz for an 8 Gbps data rate and 200 MHz for 6.4 Gbps.
- QPI Link Detection
The Intel QPI physical layer uses a TX based detect scheme. Each TX lane contains a link detect circuit on each TXP and TXN.
During QPI link detecting, the transmitter driver will be tri-stated to avoid interference.
Use the Native PHY IP core to implement QPI for a low latency requirement.
The Native PHY IP core provides direct access to the PMA from the FPGA fabric in PMA Direct mode. Consequently, the latency for transmitted and received data is very low.
Use the following steps to implement QPI with the necessary options and settings, using the Native PHY IP core:
- Configure the Native PHY IP core
After the Stratix V Transceiver Native PHY IP core opens in the MegaWizard™ Plug-In Manager, the General tab and block diagram appear. The General tab contains the general settings for the Native PHY IP core.
For example, design an 8 Gbps QPI as a full-width link using the Datapath Options.
- Select Enable TX datapath and Enable RX datapath.
- Set the Number of data channels to 20.
- Set the Bonding mode to fb_compensation.
- In the PMA tab, input the Data rate as 8000 Mbps.
- In PMA Direct Options, set the PMA direct interface width to 32.
- In the TX PLL 0 tab, select the PLL type as ATX, and set the Reference clock frequency to 250.0 MHz.
- In RX CDR Options, set the Selected CDR reference clock frequency to 250.0 MHz.
- In PMA Optional Ports, enable the ports for the QPI
- Click Finish in the MegaWizard Plug-In Manager.
- Enable the QPI Setting for the
Open the <project_name> .qsf file and input the following settings.
- set_instance_assignment -name XCVR_IO_PIN_TERMINATION 85_OHMS -to tx_serial_data
- set_instance_assignment -name XCVR_IO_PIN_TERMINATION 85_OHMS -to rx_serial_data
- set_instance_assignment -name XCVR_RX_QPI_ENABLE ON -to rx_serial_data
- set_instance_assignment -name XCVR_TX_QPI_EN ON -to tx_serial_data
DC Coupling Support
- set_instance_assignment -name XCVR_TX_VCM_CTRL_SRC DYNAMIC_CTL -to tx_serial_data
- set_instance_assignment -name XCVR_RX_INPUT_VCM_SEL LOW_VCM -to rx_serial_data
Note: For more information about QSF settings, refer to the Quartus Settings File Reference Manual.
- set_instance_assignment -name XCVR_TX_RX_DET_OUTPUT_SEL RX_DET_QPI_OUT -to tx_serial_data
- Link the Detection Design Flow
To enable RX link detection at the transmitter side, the transmitter driver must be set as tri-state. During the normal data transferring state, the transmitter driver must be enabled.
The rtx_pdb bit is used to control the transmitter buffer in tri-state. It can be accessed through the Streamer mode 3 in the transceiver reconfiguration controller.
Bit of rtx_pdb must be set to 0 before the link detection function is triggered. Writing a 1 to the rtx_pdb bit will set the transmitter buffer in normal mode. The other bits at this address cannot be modified.
Use the procedure below to set the transmitter driver to tri-state using Streamer mode 3.
To set the transmitter driver to tri-state:
- Ensure that the transceiver reconfiguration controller is correctly connected to the Native PHY IP core.
- Enable the .MIF streamer module by selecting the Enable channel/PLL reconfiguration option in the transceiver reconfiguration controller.
- Write the logical channel number to address 0x38.
- Write the MIF mode 0xC to address 0x3A.
- Write the rtx_pdb address 0x25A to address 0x3B.
- Write the Control and status register with a value of 0xE to address 0x3A to initiate a read.
- Read address 0x3c.
- With the data obtained from step 7, perform a RMW with the 15-bit data pattern that selects the rtx_pdb bit.
- Write the data pattern generated from step 8 to address 0x3C.
Write the Control and status register with a value of
0xD to address
After changing rtx_pdb to 0 to set the transmitter driver in tri-state, tx_pma_rxfound will go high after asserting tx_pma_txdetectrx and tx_pma_qpipullup, if the RX link exists with a 42.5Ω termination, as shown in the following figure.
|December 2015||2015.12.17||Added a link to the Quartus Settings File Reference Manual in the "Using the Native PHY IP Core for QPI" section.|