I/O timing information is crucial for early analysis during PCB board design stages. Generate timing parameters to help you adjust the timing budget of your design, considering I/O standards and pin placement. The relevant I/O timing information parameters are: input setup time tsu, input hold time th, and clock to output delay tco.
Generating I/O timing information includes the following steps:
- Create a simple D flipflop (DFF) design project that targets the device for analysis.
- Assign the I/O standard and pin location constraints.
- Run compilation and timing analysis.
- Determine tsu, th, and tco value.
This document provides both GUI and script-based generation examples.
Input setup time (tsu)
Data delay from input pin to input register, plus the micro setup time of the input register, minus the clock delay from input pin to input register
Input hold time (th)
Clock delay from input pin to input register, minus data delay from input pin to input register, plus micro hold time of the input register
Clock to output delay (tco)
|Delay from clock pin to I/O output register, plus register clock to output delay, plus delay from output register to output pin|
- Open or create a new Quartus® Prime project.
- Click Assignments > Device and specify the target device.
- Click New and create a BlockDiagram/Schematic File.
To add components to the
schematic, click on the Symbol Tool.
Figure 2. Symbol Button on Schematic Editor
- Under Name, type DFF, and click OK. Click in the Block Editor to insert a DFF symbol.
Add input, clock, and output pins. Connect pins to the
Figure 3. DFF with Pin Connections
- Click Processing > Start > Start Analysis and Synthesis.
- Click Assignments > Pin Planner.
Assign pin location and I/O standard constraints according to
your design specifications.
Figure 4. Pin Locations and I/O Standards Assignments in Pin Planner
- To compile the design, click Processing > Start Compilation. The Compiler generates all timing information during processing.
- Click Tools > TimeQuest Timing Analyzer.
In the Task pane,
double-click Update Timing Netlist. The timing netlist updates with full compilation
timing information that accounts for constraints.
Figure 5. Task Pane in TimeQuest Timing Analyzer
Under Set Operating
Conditions, select either Slow 900 mV
100C Model or Fast 900mV 100C
Figure 6. Set Operating Conditions in TimeQuest Timing Analyzer
- Click Report > Datasheet > Report Datasheet.
Figure 7. Datasheet Report on TimeQuest Timing AnalyzerThe Report pane displays the Setup Times, Hold Times, and Clock to Output Times reports.
- Click each report to view the Rise and Fall parameter values.
- For a conservative approach, select the maximum absolute value.
Determining I/O Timing Parameters from Datasheet Report
In the following example Setup Times report, the fall time is greater that the Rise time, therefore tsu=tfall .
In the following example Hold Times report, the absolute value of the fall time is greater that absolute value of the rise time, therefore th=tfall .
In the following example Clock to Output Time report, the absolute value of the fall time is greater that absolute value of the rise time, therefore tco=tfall .
Follow these steps to generate I/O Timing information for an Arria® 10 device reflecting multiple I/O standards:
- In an internet browser, type http://www.alterawiki.com/wiki/Device_I/O_Timing_Information_Generation in the address field.
- Click the Arria 10 IO Timing Extraction Script link, then click A10_vversion.tgz to download the file.
- Extract the contents of the file in your computer. Example: tar –zxvf A10_v1p2.tgz. The a10 folder appears.
Change directory to a10.
The a10 directory contains one or more subfolders with names corresponding to device types, such as a10_ax_r4_f40. This is the script for the Arria® 10 GX device with 66 transceiver count, package type F40.
- Change directory to a10/a10_ax_r4_f40/.
To run the script, type quartus_sta –tR
Wait for completion. The script execution may take 8 hours or more, because each change on I/O standard or pin location requires design recompilation.
Initial release of the document.