- Avalon® Streaming (Avalon-ST) interfaces
- DSP Builder for Intel® FPGAs ready
- Testbenches to verify the IP core
- IP functional simulation models for use in Intel-supported VHDL and Verilog HDL simulators
High-performance fully parameterizable encoder or decoder for error detection and correction:
- Number of symbols per codeword
- Number of check symbols per codeword
- Number of parallel input bits
Intel offers the following device support levels for Intel FPGA IP cores:
- Advance support—the IP core is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution.
- Final support—Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. You can use it in production designs.
|Arria® II GX||Final|
|Arria II GZ||Final|
|Intel® Arria® 10||Final|
|Intel® Cyclone® 10||Final|
|Intel® MAX® 10 FPGA||Final|
|Stratix® IV GT||Final|
|Stratix IV GX/E||Final|
|Intel® Stratix® 10||Advance|
|Other device families||No support|
|Release Date||Novermber 2017|
|Ordering Code||IP-BCH (IPR-BCH)|
Intel verifies that the current version of the Quartus Prime software compiles the previous version of each IP core. Intel does not verify that the Quartus Prime software compiles IP core versions older than the previous version. The Intel FPGA IP Release Notes lists any exceptions.
The Intel® Quartus® Prime software installs IP cores in the following locations by default:
|<drive>:\intelFPGA_pro\quartus\ip\altera||Intel® Quartus® Prime Pro Edition||Windows®|
|<drive>:\intelFPGA\quartus\ip\altera||Intel® Quartus® Prime Standard Edition||Windows|
|<home directory>:/intelFPGA_pro/quartus/ip/altera||Intel® Quartus® Prime Pro Edition||Linux®|
|<home directory>:/intelFPGA/quartus/ip/altera||Intel® Quartus® Prime Standard Edition||Linux|
- Simulate the behavior of a licensed Intel® FPGA IP core in your system.
- Verify the functionality, size, and speed of the IP core quickly and easily.
- Generate time-limited device programming files for designs that include IP cores.
- Program a device with your IP core and verify your design in hardware.
Intel® FPGA IP Evaluation Mode supports the following operation modes:
- Tethered—Allows running the design containing the licensed Intel® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel® Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel® Quartus® Prime software, and requires no Intel® Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
- Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel® Quartus® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.
When the evaluation time expires for any licensed Intel® FPGA IP in the design, the design stops functioning. All IP cores that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.
You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.
Intel® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Self-Service Licensing Center or contact your local Intel FPGA representative.
The Intel® FPGA Software License Agreements govern the installation and use of licensed IP cores, the Intel® Quartus® Prime design software, and all unlicensed IP cores.
For IP cores, the untethered time-out is 1 hour; the tethered time-out value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus Prime software uses Intel® FPGA IP Evaluation Mode Files (.ocp) in your project directory to identify your use of the Intel® FPGA IP Evaluation Mode evaluation program. After you activate the feature, do not delete these files..When the evaluation time expires, the data output port data_out goes low
- Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
- Type in the Search field to locate any full or partial IP core name in IP Catalog.
- Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation.
- Click Search for Partner IP to access partner IP information on the web.
The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Intel® Quartus® Prime IP file (.ip) for an IP variation in Intel® Quartus® Prime Pro Edition projects.
The parameter editor generates a top-level Quartus IP file (.qip) for an IP variation in Intel® Quartus® Prime Standard Edition projects. These files represent the IP variation in the project, and store parameterization information.
- Create or open an Intel® Quartus® Prime project (.qpf) to contain the instantiated IP variation.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears.
- Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named <your_ip> .ip. Click OK. The parameter editor appears.
Set the parameter values in the parameter editor and view the
block diagram for the component. The Parameterization Messages tab at the bottom displays any errors
in IP parameters:
Note: Refer to your IP core user guide for information about specific IP core parameters.
- Optionally, select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
- Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
- To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
and instantiating your IP variation, make appropriate pin assignments to
Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.
|Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file.|
|<your_ip>.cmp||The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files.|
|<your_ip>_generation.rpt||IP or Platform Designer generation log file. Displays a summary of the messages during IP generation.|
|<your_ip>.qgsimc (Platform Designer systems only)||
Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.
|<your_ip>.qgsynth (Platform Designer systems only)||
Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.
Contains all information to integrate and compile the IP component.
|<your_ip>.csv||Contains information about the upgrade status of the IP component.|
A symbol representation of the IP variation for use in Block Diagram Files (.bdf).
Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize.
|<your_ip>.ppf||The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner.|
|<your_ip>_bb.v||Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox.|
|<your_ip>_inst.v or _inst.vhd||HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.|
|<your_ip>.regmap||If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.|
Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system.
During synthesis, the Intel® Quartus® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system slaves, Platform Designer accesses the registers by name.
|<your_ip>.v <your_ip>.vhd||HDL files that instantiate each submodule or child IP core for synthesis or simulation.|
Contains a msim_setup.tcl script to set up and run a ModelSim simulation.
Contains a Riviera*-PRO script rivierapro_setup.tcl to setup and run a simulation.
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.
Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS MX* simulation.
Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.
|/submodules||Contains HDL files for the IP core submodule.|
|<IP submodule>/||Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates.|
The Intel® Quartus® Prime software provides integration with many simulators and supports multiple simulation flows, including your own scripted and custom simulation flows. Whichever flow you choose, IP core simulation involves the following steps:
- Generate simulation model, testbench (or example design), and simulator setup script files.
- Set up your simulator environment and any simulation scripts.
- Compile simulation model libraries.
- Run your simulator.
This IP core supports DSP Builder for Intel® FPGAs. Use the DSP Builder for Intel® FPGAs flow if you want to create a DSP Builder for Intel® FPGAs model that includes an IP core variation; use IP Catalog if you want to create an IP core variation that you can instantiate manually in your design.
You can parameterize the BCH IP core as an encoder or a decoder. The encoder receives data packets and generates the check symbols; the decoder detects and corrects errors.
The ready signal indicates that the encoder can accept incoming stream. On the clk rising edge, if the encoder ready signal is high, send input data stream via data_in port and assert load high to indicate valid input data. Assume the full message word needs X clock signals. When this input process reaches X-1 clock cycles, the encoder ready signal goes low. At the next clk rising edge, the encoder accepts the input from data_in port, and the encoder receives the full message word. Before the ready signal returns to high again, the encoder does not accept new input data. When valid_outt signal is asserted high, output encoded codeword is valid at the data_out port. At the first clock cycle where the output data is valid, sop_out is asserted high for only one cycle, indicating the start of packet. The IP core has forward and back pressure, which you can control with the ready and sink_ready signal. Assert the sop_in and eop_in signals correctly at the clock cycle, i.e. the first and last clock cycle of the input codeword.
The BCH IP core supports shortened codewords. A shortened codeword contains fewer symbols than the maximum value of N, which is 2M –1, where N is the total number of symbols per codeword and M is the number of bits per symbol. A shortened codeword is mathematically equivalent to a maximum-length code with the extra data symbols at the start of the codeword set to 0. For example, (220,136) is a shortened codeword of (255,171). Both of these codewords use the same number of check symbols, 11. To use shortened codewords with the decoder, use the parameter editor to set the codeword length to the correct value.
The received encoded codeword may differ from the original codeword because of noise in the channel. The decoder detects errors using several polynomials to locate the error location and the error value. When the decoder obtains the error location and value, the decoder corrects the errors in a codeword, and sends the codeword to the output.
The codeword starts when you assert the load signal and the sop_in signal.The decoder accepts the data at data_in as valid data. The codeword ends when you assert the eop_in signal. For a 1-channel codeword, assert the sop_in and eop_in signals for one clock cycle. When the decoder deasserts the ready signal, the decoder cannot process any more data until it asserts the ready signal again.
At the output, the operation is identical. When the decoder asserts the valid_out signal and the sop_out signal, the decoder provides valid data on data_out. The decoder asserts the sop_out signal and the eop_out signal to indicate the start and end of a codeword. The decoder automatically detects and corrects errors in a codeword and asserts the number_of_errors signal when it encounters a non-correctable codeword. The decoder outputs the full codeword including the check symbols, which you should remove.
The ready signal indicates that the decoder can accept an incoming stream. On clk rising edge, if the encoder ready signal is high, send input data stream via data_in and assert load high to indicate valid input data. When valid_out is asserted high, the output decoded word is valid at the data_out port. The number_of_errors shows the number of errors the IP core detects. At the first clock cycle where the output data is valid, sop_out is asserted high for only one cycle, indicating the start of output packet. The IP core has forward and back pressure, which you controll with the ready signal and sink_ready signal. Assert the sop_in and eop_in signals correctly at the clock cycle, i.e. the first and last clock cycle of the input codeword.
|Parameter||Legal Values||Default Value||Description|
|BCH module||Encoder or Decoder||Encoder||Specify an encoder or a decoder.|
|Number of bits per symbol (m)||3 to 14 (encoder or 6 to 14 (decoder)||14||Specify the number of bits per symbol.|
|Codeword length (n)||parity_bits+1 : 2m-1||8,784||Specify the codeword length. The decoder accept a new symbol every clock cycle if 6.5R < N. If N>=6.5R+1, the decoder shows continuous behavior.|
|Error correction capacity (t)||Range derived from m. For the decoder, the wizard caps the range between 8 and 127.||40||Specify the number of bits to be corrected.|
|Parity bits||–||560||Shows the number of parity bits in the codeword. The wizard derives this parameter from t.|
|Message length (k)||–||8,224||Shows the number of message bits in the codeword. The wizard derives this parameter from t and n.|
|Primitive polynomial||–||17,475||Shows the primitive polynomial. derived from the choice of m.|
|Parallel input data width||Encoder: 1 to min(parity_bits, k-1). Decoder:
||20||The number of bits to input every clock cycle.|
|clk||clk||Input||The main system clock. The whole IP core operates on the rising edge of clk .|
|reset||reset_n||Input||An active low signal that resets the entire system when asserted. You can assert this signal asynchronously. However, you must deassert it synchronous to the clk_clk signal. When the IP core recovers from reset, ensure that the data it receives is a complete packet.|
|ready||ready||Output||Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge.|
|data_in||data||Input||Data input for each codeword, symbol by symbol. Valid only when you assert the in_valid signal.|
|data_out||data||Output||Contains decoded output when the IP core asserts the out_valid signal. The corrected symbols are in the same order that they are entered.|
|eop_in||eop||Input||End of packet (codeword) signal.|
|eop_out||eop||Output||End of packet (codeword) signal. This signal indicates the packet boundaries on the data_in bus. When the IP core drives this signal high, it indicates that the end of packet is present on the data_in bus. The IP core asserts this signal on the last transfer of every packet.|
|in_error||error||Input||Error signal. Specifies if the input data symbol is an error and whether the decoder can consider it as an erasure. Erasures-supporting decoders only.|
|load||valid||Input||Data valid signal to indicate the validity of the data signals. When you assert the in_valid signal, the Avalon-ST data interface signals are valid. When you deassert the in_valid signal, the Avalon-ST data interface signals are invalid and must be disregarded. You can assert the in_valid signal whenever data is available. However, the sink only captures the data from the source when the IP core asserts the in_ready signal.|
|number_of_errors||error||Output||Indicates the number of errors (decoder only). Valid when the IP core asserts eop_out .|
|sop_in||sop||Input||Start of packet (codeword) signal.|
|sop_out||sop||Output||Start of packet (codeword) signal. This signal indicates the codeword boundaries on the data_in bus. When the IP core drives this signal high, it indicates that the start of packet is present on the data_in bus. The IP core asserts this signal on the first transfer of every codeword.|
|sink_ready||ready||Input||Data transfer ready signal to indicate that the downstream module is ready to accept data. The source provides new data (if available) when you assert the sink_ready signal and stops providing new data when you deassert the sink_ready signal. If the source is unable to provide new data, it deasserts valid_out for one or more clock cycles until it is prepared to drive valid data interface signals.|
|valid_out||valid||Output||Data valid signal. The IP core asserts the valid_out signal high, whenever a valid output is on data_out ; the IP core deasserts the signal when there is no valid output on data_out .|
- Input: in[0 to data width of data_in]
- Output: out[0 to data width of data_out]
- Input: in[0 to data width of data_in]
- Output: out [0 to data width+number_errors | data_out]
The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source. The Avalon-ST interface supports packet transfers with packets interleaved across multiple channels.
Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready, and valid signals. Avalon-ST interfaces can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels. The Avalon-ST interface inherently synchronizes multichannel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic.
Avalon-ST interfaces support backpressure, which is a flow control mechanism where a sink can signal to a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when it has congestion on its output.
|2015.10.01||15.1||Added product ID and ordering code.|