High-density FPGAs incorporate embedded silicon features that can implement complete systems inside an FPGA, creating a system on a programmable chip (SOPC) implementation. Embedded silicon features such as embedded memory, DSP blocks, and embedded processors are ideally suited for implementing DSP functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), correlators, equalizers, encoders, and decoders.
The embedded DSP blocks provide functionality such as addition, subtraction, and multiplication, which are common arithmetic operations in DSP functions. Generally, Altera FPGAs offer much more multiplier bandwidth than DSP processors, which only offer a limited number of multipliers.
One determining factor of the overall DSP bandwidth is the multiplier bandwidth, therefore the overall DSP bandwidth of FPGAs can be much higher using FPGAs than with DSP processors.
Many DSP applications use external memory devices to manage large amounts of data processing. The embedded memory in FPGAs meets these requirements and also eliminates the need for external memory devices in some cases.
Embedded processors in FPGAs provide versatile system integration because of flexible partitioning of the system between hardware and software. You can implement the system’s software components in the embedded processors and implement the hardware components in the FPGA's general logic resources. Altera devices provide a choice between embedded soft core processors and embedded hard core processors.
You can implement soft core processors such as the Nios® II embedded processor in FPGAs and add multiple system peripherals. The Nios® II processor supports a user-determinable multimaster bus architecture that optimizes the bus bandwidth and removes potential bottlenecks found in DSP processors. You can use multimaster buses to define as many buses and as much performance as needed for a particular application. Off-the-shelf DSP processors make compromises between size and performance when they choose the number of data buses on the chip, potentially limiting performance.
Soft embedded processors in FPGAs provide access to custom instructions such as the MUL instruction in Nios® II processors that can perform a multiplication operation in two clock cycles using hardware multipliers. FPGA devices provide a flexible platform to accelerate performance-critical functions in hardware because of the configurability of the device’s logic resources. DSP processors have predefined hardware accelerator blocks, but FPGAs can implement hardware accelerators for each application, allowing the best achievable performance from hardware acceleration. You can implement hardware accelerator blocks with parameterizable IP functions or from scratch using HDL.
Altera offers many IPs for DSP design on FPGAs. You can parameterize Altera DSP IP for the most efficient hardware implementation and to provide maximum flexibility. You can easily port the IP to new FPGA families, leading to higher performance and lower cost. The flexibility of programmable logic and soft IP allows you to quickly adapt your designs to new standards without waiting for long lead times usually associated with DSP processors.
Embedded processors and hardware acceleration offer the flexibility, performance, and cost effectiveness in a development flow that is familiar to software developers. You can combine a software design flow with hardware acceleration. In this flow, you first profile C code and identify the functions that are the most performance critical. Then, you can use Altera's DSP IP or develop your own custom instructions to accelerate those tasks in the FPGA. You can run the system control code with the other nonperformance-critical DSP algorithms on a Nios® II embedded processor. Altera also provides system integration tools such as Platform Designer for system-level partitioning and interconnection. You can use Platform Designer to build entire hardware systems by combining the embedded processor, such as a Nios® II embedded processor, with other system peripherals and IP.
You can use an HDL-based hardware design flow to develop a pure hardware implementation of a DSP system. Altera provides a complete set of FPGA development tools including the Intel® Quartus® Prime and interfaces to other EDA tools such as Synopsys, Synplify, and Precision Synthesis. These tools enable hardware design, simulation, debug, and in-system verification of the DSP system. You can also follow the DSP Builder for Intel® FPGAs design flow and implement hardware-only DSP systems in FPGAs without learning HDL.
The DSP Builder for Intel® FPGAs standard blockset is a legacy product. Altera recommends you do not use it for new designs, except as a wrapper for advanced blockset designs.
DSP Builder for Intel® FPGAs is interoperable with other Simulink blocksets. In particular, you can use the basic Simulink blockset to create interactive testbenches. The automatic testbenches allows you to compare Simulink simulation results with the output of the ModelSim simulator that simulates the HDL generated for your DSP Builder design.
You can run the ModelSim simulator from within DSP Builder for Intel® FPGAs, if the ModelSim executable is in your path. You can use a script to integrate between the DSP Builder for Intel® FPGAs advanced blockset and the ModelSim simulator. The automatic testbench flow runs a test and returns a result indicating whether or not the outputs match.
Intel® Quartus® Prime
The advanced blockset allows you to build high-speed, high-performance DSP datapaths. In most production designs there is an RTL layer surrounding this datapath to perform interfacing to processors, high speed I/O, memories, and so on. To complete the design, use Platform Designer or RTL to assign board level components. Intel® Quartus® Prime can then complete the synthesis and place-and-route process. You can automatically load a design into Intel® Quartus® Prime by clicking on the Run Quartus Prime block in the top-level model.
DSP Builder for Intel® FPGAs creates a conduit interface and hw.tcl file for each advanced blockset design. It creates a memory-mapped interface only if the design contains interface blocks or external memory blocks. It can also create an Avalon® Streaming interface. The hw.tcl file can expose the processor bus for connection in Platform Designer. A DSP Builder for Intel® FPGAs advanced blockset subsystem is available from the System Contents tab in Platform Designer after you add the path to the hw.tcl file to the Platform Designer IP search path
Ensure at least one version of The MathWorks MATLAB and Simulink tool is available on your workstation before you install DSP Builder for Intel® FPGAs. You should use the same version of the Intel® Quartus® Prime software and DSP Builder for Intel® FPGAs. DSP Builder for Intel® FPGAs only supports 64-bit versions of MATLAB.
From v18.0, DSP Builder for Intel® FPGAs advanced blockset is available for Intel® Quartus® Prime Pro Edition and Intel® Quartus® Prime Standard Edition. DSP Builder for Intel® FPGAs standard blockset is only available for Intel® Quartus® Prime Standard Edition.
|Version||MATLAB Supported Versions|
|DSP Builder Standard Blockset||DSP Builder Advanced Blockset|
|Intel® Quartus® Prime Standard Edition||Intel® Quartus® Prime Pro Edition|
The Intel® Quartus® Prime software recommends you specify a path to an LM_LICENSE_FILE variable, but it also allows you to use an explicit path to a license file. However, DSP Builder for Intel® FPGAs allows you to specify a path to only an LM_LICENSE_FILE variable.
|2017.05.02||17.0||Updated MATLAB version support for DSP Builder v17.0.|
|2015.05.01||15.0||Updated MATLAB version support for DSP Builder v15.0.|
|December 2014||14.1||Updated MATLAB version support for DSP Builder v14.1.|
|June 2014||14.0||Updated MATLAB version support for DSP Builder v14.0.|
|November 2013||13.1||Updated MATLAB version support for DSP Builder v13.1.|
|May 2013||13.0||Updated MATLAB version support for DSP Builder v13.0.|
|November 2012||12.1||Updated MATLAB version support.|
|November 2011||11.1||Updated MATLAB version support.|