The IP core offers two algorithms to generate the Gaussian sequence: central-limit theorem (CLT) components and Box-Muller transform. The CLT components make use of a mixture of Irwin-hall distribution (the distribution of sum of uniform distribution) to approximate the Gaussian distribution. The classic Box-Muller transform is for reference, as it is more costly to implement on hardware and has only average random sequence quality.
- Uniformly distributed integer number
- Uniformly distributed floating point number
- Floating point number under Gaussian distribution
Altera offers the following device support levels for Altera FPGA IP cores:
- Advance support—the IP core is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—Altera verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution.
- Final support—Alteraverifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. You can use it in production designs.
|Arria® II GX||Final|
|Arria II GZ||Final|
|MAX® 10 FPGA||Final|
|Stratix® IV GT||Final|
|Stratix IV GX/E||Final|
|Other device families||No support|
|Parameters||ALMs||Memory Bits||RAM Blocks||DSP Blocks||fMAX (MHz)|
|Uniform distribution integer||113||0||0||0||693|
|Uniform distribution float||308||0||0||0||484|
|Normal distribution with central limit transform (CLT) components||3,469||4096||1||6||405|
|Normal distribution with Box-Muller||5,511||452,952||29||40||298|
|rand_num_ready||Input||Stalls the IP core for backpressure.|
|rand_num_valid||Output||Indicates valid output.|
|Type of the generator||Uniform distribution (integer), uniform distribution (float), normal distribution (float)||The type of the random number generator.|
|Generator architecture||Central limit components (recommended) or Box Muller||The algorithm to use for the Gaussian distribution generator (normal distribution only).|
|Seed selection||Auto or manaul||Set the seed manually or automatically.|
|Value of the seed||1 to 2147483647; default: 68997764||Manually input the seed for the random sequence, in the format of an integer.|
|May 2015||2016.05.02||Initial release.|
|February 2017||2017.02.21||Corrected rand_num_data and rand_num_valid signals to be output.|