If a release note is not available for a specific IP core version, the IP core has no changes in that version. Information on the latest update releases is in the Altera Complete Design Suite Update Release Notes.
|Added support for multiple (2, 3, or 4) data interfaces
in full-width variations.
||The IP core has new signals to support multiple data interfaces for full-width variations.||You must upgrade to the 16.0 version of the IP core if you use the Quartus® Prime software v16.0.|
|Added new Response re-ordering parameter for full-width variations, to specify that the IP core should return responses on each data response interface in the order it received the original requests on the corresponding data request interface.||When you turn on this new option, the IP core implements tag management internally, and the tags are not visible on the data interfaces.|
|Expanded list of supported transactions by adding non-power of two payload sizes for READ, WRITE, and Posted WRITE transactions in full-width variations.||Full-width variations now support all transaction types that half-width variations support.|
|Changed name of Enable Altera Debug Master Endpoint (ADME) parameter to Enable ADME and Optional Reconfiguration Logic. Added list of PHY debugging features the parameter sets.||The IP core no longer supports the ODI acceleration logic feature.|
|Restricted list of allowed values for the CDR reference clock parameter to standard HMC reference clock frequencies.||Supported CDR clocks:
|Added new data path response interface signal dp<n>_rsp_errstat[6:0].||This signal holds the value of the ERRSTAT field of the response packet from the external HMC.|
|Removed pll_powerdown output signal.|
|Updated description of dp<n>_rsp_error signal to indicate that the IP core now maintains the value of dp<n>_rsp_error for the duration of a multi-cycle transaction. Previously this behavior was not guaranteed.|
|Added new Limit Outstanding FLITs feature for full-width variations to mitigate read response congestion. Added new LIMIT_OUTSTANDING_PACKET register to control the feature.||The IP core supports the Limit Outstanding FLITs feature for full-width variations.|
|Added software control for reset,
link reinitialization, fatal error recovery, and power management.
Added the following fields to the CONTROL register:
|Design Example Errata|
|During compilation, the
Quartus® Prime Pro Edition software issues the following
Critical Warning(18226): Physical Synthesis has been replaced by Spectra-Q Physical Synthesis for the Arria 10 device family, but there are still Physical Synthesis assignments in the project's Quartus Settings File (.qsf). Support for these assignments will be discontinued in the next release of the Quartus Prime software.
|This message is a warning, not a critical warning.|
|The design example asserts the registers_loaded trigger too late, causing an Init Continue ERI status 0x12 (initialization timeout).||Designers can ignore the initialization error.|
|After you make the design example simulation scripts, the directory structure contains directories for VCSMX and Aldec, however, the IP core does not support these simulators.|
|During compilation, the Fitter may issue base clock assignment warnings.||Designers can ignore the Fitter base clock assignment warning.|
|The design example contains unconstrained output ports.||Designers can ignore these unconstrained ports.|
ADME feature. When you turn on the Enable Altera Debug Master
Endpoint (ADME) parameter the IP core enables an
additional Arria 10 Transceiver PHY IP core feature. In the 15.0
release, turning on the parameter turned on these Arria 10 PHY
In the 15.1 release, the parameter also turns on this Arria 10 PHY feature:
|This feature does not affect the top-level signals of the IP core.||You must upgrade to the 15.1 version of the IP core if you use the Quartus Prime software v15.1.|
|Initial public release.|