Cyclone® 10 LP devices provide a high density sea of programmable gates, on-board resources, and general purpose I/Os. These resources satisfies the requirements of I/O expansion and chip-to-chip interfacing. The Cyclone® 10 LP architecture suits smart and connected end applications across many market segments:
- Industrial and automotive
- Broadcast, wireline, and wireless
- Compute and storage
- Government, military, and aerospace
- Medical, consumer, and smart energy
The free but powerful Quartus® Prime Lite Edition software suite of design tools meets the requirements of several classes of users:
- Existing FPGA designers
- Embedded designers using the FPGA with Nios® II processor
- Students and hobbyists who are new to FPGA
Advanced users who require access to the full IP Base Suite can subscribe to the Quartus® Prime Standard Edition or purchase the license separately.
Internal memory blocks
|Embedded multiplier blocks||
Phase-locked loops (PLLs)
General-purpose I/Os (GPIOs)
|SEU mitigation||SEU detection during configuration and operation|
|Logic Elements (LE)||6,272||10,320||15,408||24,624||39,600||55,856||81,264||119,088|
|18 × 18 Multiplier||15||23||56||66||126||156||244||288|
|Size||8 mm × 8 mm||14 mm × 14 mm||19 mm × 19 mm||22 mm × 22 mm||23 mm × 23 mm||29 mm × 29 mm|
|Ball Pitch||0.5 mm||0.8 mm||0.8 mm||0.5 mm||1.0 mm||1.0 mm|
- The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Devices with lesser I/O resources in the same path have lighter shades.
- To achieve full I/O migration across devices in the same migration path, restrict I/O usage to match the device with the lowest I/O count.
The LAB consists of 16 logic elements (LE) and a LAB-wide control block. An LE is the smallest unit of logic in the Cyclone® 10 LP device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables.
You can control the operation of the embedded multiplier blocks using the following options:
- Parameterize the relevant IP cores with the Quartus® Prime parameter editor
- Infer the multipliers directly with VHDL or Verilog HDL
Intel and partners offer popular DSP IPs for Cyclone® 10 LP devices, including:
- Finite impulse response (FIR)
- Fast Fourier transform (FFT)
- Numerically controlled oscillator (NCO) functions
For a streamlined DSP design flow, the DSP Builder tool integrates the Quartus® Prime software with MathWorks Simulink and MATLAB design environments.
You can configure the M9K memory blocks as RAM, FIFO buffers, or ROM.
|Operation Modes||Port Widths|
|Single port||×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36|
|Simple dual port||×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36|
|True dual port||×1, ×2, ×4, ×8, ×9, ×16, and ×18|
- Up to 20 GCLK networks that drive throughout the device
- Up to 15 dedicated clock pins
- Up to four general purpose PLLs with five outputs per PLL
The PLLs provide robust clock management and synthesis for the Cyclone® 10 LP device. You can dynamically reconfigure the PLLs in user mode to change the clock phase or frequency.
Cyclone® 10 LP devices offer highly configurable GPIOs with these features:
- Support for over 20 popular single-ended and differential I/O standards.
- Programmable bus hold, pull-up resistors, delay, and drive strength.
- Programmable slew-rate control to optimize signal integrity.
- Calibrated on-chip series termination (RS OCT) or driver impedance matching (RS) for single-endd I/O standards.
- True and emulated LVDS buffers with LVDS SERDES implemented using logic elements in the device core.
- Hot socketing support.
You can use EPCS or EPCQ (AS x1) flash configuration devices to store configuration data and configure the Cyclone® 10 LP FPGAs.
- Cyclone® 10 LP devices support 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration schemes.
- The single-event upset (SEU) mitigation feature detects cyclic redundancy check (CRC) errors automatically during configuration and optionally during user mode1.
|Configuration Scheme||Configuration Method||Decompression||Remote System Upgrade|
|Active serial (AS)||Serial configuration device||Yes||Yes|
|Passive serial (PS)||External host with flash memory||Yes||Yes|
|Fast passive parallel (FPP)||External host with flash memory||—||Yes|
|JTAG||External host with flash memory||—||—|
Cyclone® 10 LP devices are built on optimized low-power process:
- Available in two core voltage options: 1.2 V and 1.0 V
- Hot socketing compliant without needing external components or special design requirements
To accelerate your design schedule, combine Intel® Cyclone® 10 LP FPGAs with Enpirion® Power Solutions. Intel’s ultra-compact and efficient Enpirion® PowerSoCs are ideal for meeting Cyclone® 10 LP power requirements. Enpirion® PowerSoCs integrate most of the required components to provide you fully-validated and straightforward solutions with up to 96% efficiency. These advantages reduce your power supply design time and allow you to focus on your IP and FPGA designs.
|May 2017||2017.05.08||Initial release.|