Your FPGA has several inputs requiring power for the FPGA to operate. These inputs supply power to various resource blocks within the FPGA, including logic, RAM, digital signal processing (DSP), phase-locked loops (PLLs), clocks, I/Os, and transceivers. These resource blocks have static and dynamic power requirements that vary by your selected FPGA and utilization. Your selected FPGA does not have a fixed power requirement; your total power consumption, and your FPGA power tree, depends on your design.
You can calculate your FPGA power requirements with the Microsoft Excel-based PowerPlay Early Power Estimator (EPE) spreadsheet. You can use the PowerPlay EPE spreadsheet to estimate power consumption at any point in your design cycle, including before you have begun your design, or before your design is complete. The PowerPlay EPE spreadsheet allows you to submit estimates of how you will utilize the various resource blocks in your FPGA; once you enter your estimates, the PowerPlay EPE spreadsheet automatically estimates the required power consumption. For detailed information on using the PowerPlay EPE spreadsheet, please see the PowerPlay Early Power Estimator User Guide.
Altera® recommends switching from the PowerPlay EPE spreadsheet to the PowerPlay Power Analyzer in the Quartus® II software once your design is available. The PowerPlay Power Analyzer can access the implemented design details to produce more accurate results. For detailed information on using the PowerPlay Power Analyzer, please see PowerPlay Power Analysis in the Quartus II Handbook.
Most FPGA inputs require a voltage of ≤3.3V. Building an FPGA power tree from a low voltage input source often allows for a smaller, more efficient system. If you use an input source of 12V or higher, or if the PowerPlay Early Power Estimator (EPE) spreadsheet estimates the total FPGA current consumption is very high, Altera recommends that you use a two-stage voltage solution, where:
- A first-stage power converter converts a high voltage to a lower intermediate voltage, and
- A second-stage power converter converts the intermediate voltage to the final FPGA input voltages
The input supply voltage and voltage architecture must be determined before you select power converters.
The Report tab in the PowerPlay Early Power Estimator (EPE) spreadsheet details the expected voltage and current requirements for each FPGA power rail based on your design. The PowerPlay EPE spreadsheet indicates which FPGA power rails require a power supply in two ways:
- The FPGA input line has a non-zero value in the “Total Current (A)” column.
- For PowerPlay EPE spreadsheet versions 13.1 and later, the FPGA input line has an assigned (not grey) entry in the “Power Regulator Settings Regulator Group” column adjacent to the “Total Current (A)” column.
You must identify the power rails requiring power in your design prior to grouping the power rails together.
Refer to the Pin Connection Guidelines for your selected Altera® FPGA to determine what inputs can be grouped together; the Pin Connection Guidelines recommend a power supply block architecture for each FPGA configuration and provide details about each input pin required during hardware design.
Altera suggests power rail groupings in the Pin Connection Guidelines for each Altera FPGA, but there are two other factors to consider when grouping your power rails. First, each of the FPGA power rail inputs in a group must have the same supply voltage requirement. This limitation is important for FPGA resource blocks such as I/O inputs that might require different voltages depending on the specific interface protocols utilized in your design. For example, a PCI Express® ( PCIe® ) I/O interface might require a 3V input supply and an LVDS I/O interface might require a 2.5V input supply; while both are I/O inputs, and the Pin Connection Guidelines simplified the I/O inputs as a single VCCIO rail, these two I/O inputs must be powered by different converters.
The second power rail grouping factor to consider is power-up sequencing. Not every FPGA or system requires power-up sequencing, but many advanced FPGAs require that power is supplied to various inputs in a specific order during system power-up. You can locate the power-up sequence guidelines for your selected Altera FPGA in the device’s Pin Connection Guidelines or Handbook. If your design requires power-up sequencing, you must ensure that grouped power rail inputs meet the sequence requirements for your Altera FPGA. A power rail cannot be powered if it depends upon another rail in the same group or a rail in a later group.
Any inputs in your design can be powered individually, or can be powered in combination with another group of FPGA inputs that share their voltage and sequencing requirements.
Once you have determined your power rail input groupings, you can use the PowerPlay Early Power Estimator (EPE) spreadsheet to determine the total power required for the input group. The PowerPlay EPE spreadsheet combines the current requirements for each load by summing each FPGA input’s current requirement, as shown in the “Total Current (A)” column in the PowerPlay EPE spreadsheet Report tab. The PowerPlay EPE spreadsheet automatically sums the current requirements of the input power rail group and displays a summary on the Main spreadsheet tab. The shared input voltage and summed current of the power rail group determines the total power required for the group.
You can use the PowerPlay EPE spreadsheet to group inputs at any point in your design cycle, including before you have begun your design, or before your design is complete.
To create a power tree block diagram, use the online, cloud-based PowerPlay Power Tree Designer.
Once you determine what converters meet the minimum electrical requirements, you must prioritize your system requirements, including size, efficiency, switching frequency, power supply noise, and cost. Optimizing some parameters or resources may degrade the performance of others. For example, increasing the switching frequency allows for a smaller system size with lower switching noise in critical frequency bands, but higher switching frequency requires more DC-DC switching and reduces efficiency by generating more switching loss. The Altera® Enpirion® power solutions use special design techniques and laterally diffused metal oxide semiconductor technology to reduce loss at high switching frequencies to minimize this trade-off.
System priorities also vary depending upon the load. For example, the FPGA core power rail input (VCC) requires high power supply accuracy and low ripple to meet tight tolerance specifications, while power supply noise is a key parameter for sensitive power rails (such as transceiver voltage rails) to minimize both jitter and the bit error rate (BER).
Some power management decisions impact designs at the system level and must be considered early in the design process for successful implementation in the final system design. Some components support more advanced system power management and FPGA power reduction techniques; these components typically require special interfaces and feature sets that you should specify early in the FPGA design process. For example, you can include Enpirion® power solutions that support SmartVID in Arria® 10 device designs, or use Enpirion® digital controllers and PowerSoCs with a PMBus interface to implement system telemetry.
You can use the Report tab of the PowerPlay EPE spreadsheet to manually adjust groupings based on your design. Modifications can include: using I/O protocols at different voltages; separating sensitive rails; and implementing sequencing.
You can use the Enpirion tab to adjust the power solution recommendations based on your design priorities. Modifications can include: selecting rails to choose a low-dropout (LDO) regulator for lower noise or lower cost; and selecting devices with a “Power Good” (POK) flag for sequencing or other fault monitoring.
You can use the PowerPlay Power Tree Designer to save and share designs online, download your design’s bill of materials and netlist, check stock availability, and order components from distributors.
|October 2014||Initial release.|