If a release note is not available for a specific IP core version, the IP core has no changes in that version. Information on the latest update releases is in the Intel Quartus Prime Design Suite Update Release Notes.
|Renamed the following as per Intel rebranding:
|Added advance support for Intel® Cyclone® 10 GX devices.||The Intel® Cyclone® 10 GX devices are only available in the Intel® Quartus® Prime Pro Edition software.|
|YCbCr 4:2:0 color format is now supported.||These features are only available in the Intel® Quartus® Prime Pro Edition software.|
|The Intel® FPGA DisplayPort IP core version 17.1 conforms to Video Electronics Standards Association (VESA) DisplayPort Standard version 1.4.|
|Added data link rate support for HBR3 (8.10 Gbps). This
rate is only available in quad symbols per clock for
Arria® 10 and
Cyclone® 10 GX devices.
Note: The clock recovery module in the Intel® Arria® 10 design examples only support up to 4Kp60 resolution.
|Updated the design examples to DisplayPort SST Parallel Loopback With PCR and DisplayPort SST Parallel Loopback Without PCR.|
In previous versions of the Intel® FPGA DisplayPort design example for Intel® Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Intel® Quartus® Prime software version 17.1.
|If you are upgrading designs that have these additional constraints from the previous versions of Intel® Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information.|
|Available in both Quartus Prime Pro Edition and Quartus Prime Standard Edition.||These changes are optional. If you do not upgrade your IP core, it does not have these new features.|
|Added support for the following features:
|Added a new parameter: TX Video IM Enable. Turn on to enable the video image interface. Turn off to use the traditional HSYNC/ VSYNC/DE video input interface.|
|Multi-stream transport (MST) feature supports audio data channel.|
|The 16.1 version of the DisplayPort IP core is available only in Quartus Prime Standard Edition.||These changes are optional. If you do not upgrade your IP core, it does not have these new features.|
Multi-stream transport (MST) feature does not support audio data channel.
|Added support for multiple TX instances in software API.|
|Added new Design Example tab in the DisplayPort IP core parameter editor. The design example is for Arria 10 devices. Refer to the DisplayPort IP Core Design Example User Guide for more information.|
|Removed the Import fixed MSA parameter and the txN_msa_conduit signal. The DisplayPort source core now automatically inserts the TX main stream attribute (MSA).||These changes are optional. If you do not upgrade your IP core, it does not have these new features.|
|Added support for black video feature for DisplayPort sink core.|
|Added support for Link Quality Analysis (LQA).|
|The txN_vid_f pin is removed from the DisplayPort IP core. The IP core handles the interface internally.||These changes are optional. If you do not upgrade your IP core, it does not have these new features.|
|Updated multi-stream support:
|Added preliminary support for Arria 10 devices.||These changes are optional. If you do not upgrade your IP core, it does not have these new features.|
|Updated color support.
|Added source-supported DPCD locations.|
|Added new bits for DPTX_TEST_80BIT_PATTERN bits.|
|Removed the Link Quality Generation register bits and
combined these bits into the DPTX_TX_CONTROL register.
|Added new sink-supported DPCD location bits: TEST_REQUEST, TEST_LINK_RATE, TEST_LANE_COUNT, PHY_TEST_PATTERN, and TEST_80BIT_CUSTOM_PATTERN.|
|Added simulation testbench for Arria 10 devices.|
| Added multi-stream support (MST, 1 to
4 source and sink streams). You can access this feature using these
||These changes are optional. If you do not upgrade your IP core, it does not have these new features.|
|Added support for 4Kp60 resolution.|
|Removed support for double reference clocks—162 MHz and 270 MHz—for transceiver clocking.|
|Updated the design example with pixel clock recovery feature and 4Kp60 support.|
|Added new signals.|
|Added new source registers:
|Added new sink registers:
|Changed the value of the following register bits:
|Old Signal Name||New Signal Name||Notes|
|—||clk_cal||Calibration clock for transceiver management interface|
|—||tx_link_rate_8bits||Main link rate expressed in multiples of 270Mbps|
|—||txN_video_in (N=1,2,3)||TX signals for Stream 1, 2 and 3|
|—||rxN_video_out (N=1,2,3)||RX signals for Stream 1, 2 and 3|