If a release note is not available for a specific IP core version, the IP core has no changes in that version. Information on the latest update releases is in the Intel Quartus Prime Design Suite Update Release Notes.
When opening a Quartus Prime Pro Edition software version 16.0 or 16.1 XAUI PHY IP core design in Quartus Prime Pro Edition software version 17.0, you may encounter the following issues:
This issue only occurs when you generate the XAUI IP core from the Quartus Prime Pro Edition software. The Quartus Prime Standard Edition software is not affected by this issue.
Despite these display issues, the Perform Automatic Update function correctly performs the necessary update.
|The Quartus II software v14.1 requires that you specify a device if your IP core targets the Arria 10 device family. If you do not specify your target Arria 10 device, the IP Upgrade tool insists that your IP core requires upgrade, but does not clarify the reason.||You must ensure that you specify a device for your v13.1 Arria 10 Edition or v14.0 Arria 10 Edition IP core variation and regenerate it in the Quartus II software v14.1.|
|Added the Enable phase compensation FIFO parameter.||-|
|Added the xgmii_rx_inclk port, which is available when Enable phase compensation FIFO is enabled.||-|
|Added the pll_cal_busy_i port, which connects to the pll_cal_busy output port of the external PLL.||-|
|Added a new Arria 10 SDC constraint requirement. Refer to the "XAUI PHY TimeQuest SDC Constraint" section of the Arria 10 Transceiver PHY User Guide.||-|
|Added support for Arria 10 devices. To use the XAUI PHY IP core for Arria 10 devices, you must instantiate an external transmit PLL. You can only use the ATX PLL IP core with the XAUI PHY IP core for Arria 10 devices.||-|
|Added Enable dynamic reconfiguration parameter.||-|
|Removed the following parameters:
|Added new port to enable connectivity with an external transmit PLL and with the dynamic reconfiguration interface. Refer to the Arria 10 Transceiver PHY User Guide parameter and port descriptions.||-|
|The XAUI PHY IP core does not support NCSIM simulator. You will see an error message during elaboration.||-|
|The XAUI PHY IP core does not support VHDL. You will get a compilation error when you simulate the XAUI PHY IP core generated in VHDL. You must generate this IP core in Verilog.||-|
|Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores.||-|
|Verified in the Quartus II software v13.1||-|