The Intel® Cyclone® 10 GX FPGA Development Kit is a complete design environment that includes both hardware and software you need to develop and evaluate the performance and features of the Intel® Cyclone® 10 GX FPGA device.
Intel® Cyclone® 10 GX FPGA
- Intel® Cyclone® 10 GX FPGA device in F780 BGA package
- 780 pin, 29 mm x 29 mm BGA package
- 220K Logic Elements (LEs)
- 12 transceivers capable of 12.5 Gbps data rates
- 284 GPIOs with 118 pairs of LVDS
- Active Serial (ASx4) mode configuration with EPCQ-L
- Fast Passive Parallel (FPP) mode configuration mode by Intel® MAX® 10 PFL
- Configuration via PCIe® (CvP) x4 Gen2
- 50 MHz oscillator, LVCMOS for USB Blaster and Power Intel® MAX® 10 logic
- 50 MHz oscillator, LVCMOS for PFL control Intel® MAX® 10 logic
- 24 MHz crystal for USB-Blaster II PHY
- 50 MHz oscillator, LVCMOS for Intel® Cyclone® 10 GX FPGA core
- 100 MHz oscillator, LVCMOS for Intel® Cyclone® 10 GX FPGA user_clk
- A programmable oscillator, LVDS for tranceivers: 644.53125 MHz by default, LVDS to FPGA tranceiver
- Programmable clock generator for FPGA logic
- 21.186 MHz LVDS for EMIF, LVDS to FPGA core
- 125 MHz LVDS for transceiver of USB3.1, LVDS to FPGA transceiver
- 125 MHz for Gigabit Ethernet, LVDS to FPGA core
- 100 MHz for FPGA logic, LVCMOS to FPGA core
- 100 MHz for PCIe® system to FPGA transceiver
- User-defined reference clock input from FMC card
- 1 for FMC transceiver to FPGA transceiver
- 2 for FMC LA reference to FPGA core
- 2 for FMC clock reference to FPGA core
- One external differential input through SMA, AC coupled
- One single-ended LVCMOS clock output through SMA, DC coupled
- 12 transceivers organized in two banks
- 4 channels for PCIe® x4 Gen2
- 2 channels for 2 SFP+ supporting 10 GE
- 1 channel for USB3.1 SuperSpeed
- 5 channels for FMC card
- 1 channel of x40 DDR3 @ 933 MHz
- 10/100/1000Base-T Ethernet port with SGMII (LVDS)
- USB3.1 Type-C supporting SuperSpeed, backward compatible with USB2.0
- 2 SFP+ supporting 10GE
- FMC expansion card:
- 12G SDI: Semtech RDK-12GSRD-ALTRA00 Evaluation Board
- 8G DisplayPort: Bitec FMC DisplayPort Daughter Card
- 6G HDMI 2.0: Bitec FMC HDMI Daughter Card
- 3 User Push Buttons
- 1 User Program selecting Pushbutton
- 1 nCONFIG Pushbutton to initiate configuration
- 1 FPGA reset Pushbutton to reset the FPGA logic
- 4 User DIP Switches
- DIP switch for MSEL
- DIP switch for JTAG chain selection
- DIP switch for clock source selection
- 4 User LEDs
- 1 Power LED
- 1 Config Done LED
- PFL Load/Error LED
- PFL Program Number LED
- Ethernet LEDs
- SFP+ LEDs
Heatsink and Fan
Heatsink with fan
- 12 V power input from ATX 2 x 4 power connector
- 12 V external power adaptor input
- 12 V power input from PCIe® system
- On/Off Slide Power Switch
- On-board power measurement and management
- Adjustable FMC+ power regulator
- Power Failure Monitor
- Power-off discharge circuit
Full height PCIe® add-in card 4.376" (Height) x 7" (Length)
Ambient Temperature: 0° C to 45° C
- Recommended ambient operating temperature range: 0° C to 45° C
- Maximum ICC load current: 6 Amp
- Maximum ICC load transient percentage: 30%
- Maximum board power consumption: 75 Watts
When handling the board, it is important to observe static discharge precautions.
The Intel® Quartus® Prime design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The Intel® Quartus® Prime software delivers the highest performance and productivity for Altera® FPGAs, CPLDs, and SoCs.
Design software must enable dramatically increased design productivity in order to take advantage of devices with multi-million logic elements with increased capabilities that provide designers with an ideal platform to meet next-generation design opportunities.
The new Intel® Quartus® Prime Design Suite design software includes everything needed to design for Altera® FPGAs, SoCs and CPLDs from design entry and synthesis to optimization, verification and simulation. The Intel® Quartus® Prime Design Suite software includes an additional Spectra-Q® engine that is optimized for Intel® Stratix® 10 and future devices. The Spectra-Q® engine enables new levels of design productivity for next generation programmable devices with a set of faster and more scalable algorithms, a hierarchical database infrastructure and a unified compiler technology.
Intel® Quartus® Prime Software
The Intel® Quartus® Prime Design Suite software is available in three editions based on specific design requirements: Pro, Standard, and Lite Edition.
The Intel® Quartus® Prime Pro Edition is optimized to support the advanced features in Altera's next generation FPGAs and SoCs.
The Intel® Cyclone® 10 GX FPGA is only supported on Intel® Quartus® Prime Pro Edition. There is no paid license fee required for Intel® Cyclone® 10 GX support in Intel® Quartus® Prime Pro Edition.
Included in the Intel® Quartus® Prime Pro Edition are the Intel® Quartus® Prime software, Nios® II EDS and the MegaCore IP Library.
To install Altera® 's development tools, download the Intel® Quartus® Prime Pro Edition software from the Quartus Prime Pro Edition page from the Download Center of Altera® 's website.
- Download the development kit package from the Intel® Cyclone® 10 GX FPGA Development Kit link on the Altera® website.
- Unzip the Intel® Cyclone® 10 GX FPGA Development Kit package contents to your machine's local hard drive.
- The package creates the directory structure shown in the figure below.
The table below lists the file directory names and a description of their contents
|File Directory Name||Description of Directory Contents|
|board_design_files||Contains schematics, layout, assembly and bill of material board design files. Use these files as a starting point for a new prototype board design|
|demos||Contains demonstration applications when available|
|documents||Contains the development kit documentation|
|examples||Contains the sample design files for the development kit|
|factory_recovery||Contains the original data programmed onto the board before shipment. Use this data to restore the board with its original factory contents.|
The Intel® Cyclone® 10 GX FPGA Development Kit includes embedded Intel® FPGA Download Cable circuits for FPGA programming. However, for the host computer and board to communicate, you must install the Intel® FPGA Download Cable driver on the host computer.
Installation instructions for the Intel® FPGA Download Cable driver for your operating system are available on the Altera website.
On the Altera website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions.
To prepare and apply power to the board, perform the following steps:
In this mode, plug the board into an available PCIe® slot and connect the standard 2x4 PCIe® auxiliary power available from the PC's ATX power supply to the mating connector on the board (J12), and remove any power supply connected to J13. The PCIe® slot together with the PCIe® power is required to power the entire board with power up to 75 Watt. If ATX power is not connected, ensure that your PCIe® system can provide up to 75 Watt of power through the PCIe® slot alone. The power switch S14 is ignored when the board is used in the PCIe® .
Stand-alone evaluation board:
In this mode, plug the included power supply into the power adapter connector (J13) and the AC power cord of the power supply into a power outlet. Remove any ATX power supply that is connected from the 2x4 power connector (J12). The power switch S14 will power ON/OFF the board.
|Board Label||Switch||Default Position||Function|
|S1||S1.1||OPEN/OFF/1||Intel® Cyclone® 10 GX GX FPGA MSEL|
|S2||S2.1||CLOSE/ON/0||Select clock from Si570 for Si53307's output|
|S2.2||OPEN/OFF/1||Enable the output of Si570|
|S3||S3.1||OPEN/OFF/1||Select internal oscillator as the PLL reference of Si5332|
|S5||S5.1||OPEN/OFF/1||Enable FMC card JTAG|
|S5.2||OPEN/OFF/1||Enable Intel® Cyclone® 10 GX FPGA JTAG|
|S6||S6.1||OPEN/OFF/1||Reserved, no function defined|
|S6.2||OPEN/OFF/1||Reserved, no function defined|
|S9||S9.1||OPEN/OFF/1||User available Digital Input 0|
|S9.2||OPEN/OFF/1||User available Digital Input 1|
|S15||S15.1||OPEN/OFF/1||User available Digital Input 2|
|S15.2||OPEN/OFF/1||User available Digital Input 3|
- Intel® Cyclone® 10 GX FPGA and its peripherals
- Configuration with Intel® MAX® 10 FPGA
- Power Supply
|U1||FPGA||Intel® Cyclone® 10 GX FPGA 10CX220YF780E5G, 220K Logic Elements, 12 Transceivers, F780 BGA package|
|U2||FPGA||Intel® MAX® 10 10M08SAU169C8G for On-board Intel® FPGA Download Cable II and Power Management|
|U3||FPGA||Intel® MAX® 10 10M08SAU169C8G for PFL configuration, clock generator control and power monitoring|
|U49||Voltage Regulator||Enpirion® EM2130L-30A Step-Down DC-DC Switching Converter with Integrated Inductor, featuring Digital Control with PMBus™ v1.2 Compliant Interface, implements FPGA 0.9V Vcc|
|U50||Voltage Regulator||Enpirion® EM2130H – 30A Step-Down DC-DC Switching Converter with Integrated Inductor, Featuring Digital Control with PMBus™ v1.2 Compliant Interface, implements 3.3V intermediate power bus used by other lower voltage power rails|
Enpirion® ER2120QI - 2A Synchronous Buck
Regulator with Integrated MOSFETs, implements 5V USB VBUS of USB3.1 Type-C interface
Enpirion® ER3105DI - 500mA Wide VIN
Synchronous Buck Regulator, implements local power supply used by U49 and U50.
|U53, U54, U55, U60||Voltage Regulator||Enpirion® EN6337QI - 3A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor, implements 1.03V, 1.5V, and 1.8V power rails to FPGA|
|U56||Voltage Regulator||Enpirion® EN6347QI - 4A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor, implements voltage adjustable power rail to FPGA and FMC daughter card|
Enpirion® ER3110DI - 1A Wide VIN
Synchronous Buck Regulator, implements power supply used by U2 and U3.
|Configuration and Setup Elements|
|J9||Embedded Intel® FPGA Download Cable II||Type-B Micro USB Connector for programming and debugging the FPGA|
|J11||10-pin header||Optional JTAG direct via 10-pin header for external download cables|
Intel® Cyclone® 10 GX FPGA Configuration Mode
|S7||FPGA PGM_SEL Push Button||Press this button to cycle through different PFL loads|
|S12||FPGA nCONFIG Push Button||Press this button to trigger reconfiguration|
|S13||FPGA Reset Push Button||Press this button to reset all registers in the FPGA|
|D23||Power LED (Green)||
Power Good LED (All power rails are OK)
ON: Detected Power is Good
OFF: Detected Power is Bad
|D13||Configuration Error LED (Red)||
Config error status Indicator
ON: FPGA configuration failed
OFF: FPGA configured without error
|D14||Load LED (Green)||
Config is loading
ON: FPGA configuration is going on
OFF: FPGA configuration has finished
|D15||Configuration LED (Green)||
Config done status Indicator
ON: FPGA configured successfully
OFF: FPGA not configured
|General User Input/Output|
|S8, S10, S11||General user push buttons||Three user push buttons. Driven low when pressed.|
|D19, D20, D21, D22||User LEDs||Four user LEDs. Illuminates when driven low.|
|S9, S15||User DIP Switches||4-bit user DIP switches, low when set to ON|
|U11||50 MHz Oscillator||50 MHz crystal oscillator for logic of two Intel® MAX® 10 FPGA devices, 3.3V LVCMOS|
|Y4||50 MHz Oscillator||50 MHz crystal oscillator for general purpose logic of Intel® Cyclone® 10 GX FPGA, 1.8V LVCMOS|
|Y1||100 MHz Oscillator||100 MHz crystal oscillator for calibration and configuration of Intel® Cyclone® 10 GX FPGA, 1.8V LVCMOS|
|Y2||Programmable Oscillator||Programmable Oscillator for Intel® Cyclone® 10 GX FPGA Transceivers, LVDS|
|U7||Clock Buffer||2:1 buffer for reference clock|
|U64||Programmable clock generator||Eight channel Programmable clock generator. 4 outputs are implemented, default frequencies are 125 MHz, 21.186 MHz, 125 MHz and 100 MHz|
|U16||PCIe® x4 Golden Finger||PCIe® Gen2 x4 endpoint|
|J5, J6||SFP+||Support 10 GE SFP+ module|
|J7||FMC||5 Transceivers up to 12.5Gbps|
|J8||USB Type-C||Implements USB3.1 and USB2.0|
|U26||USB 2:1 MUX||TI HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX|
|U65||USB Redriver||TI USB1002 USB3.1 10 Gbps Dual-Channel Linear Redriver|
|U12, U13, U14||DDR3 memory||ISSI IS43TR16256A-107MBLI 256Mx16 4Gb DDR3 SDRAM|
|U4||EPCQ-L Flash||EPCQ-L 1024|
|U58||QSPI Flash||ISSI IS25WP256D-RHLE, 256Mbit|
|J12||PCIe® ATX 2x4||Auxiliary power supply of PCIe® system|
|J13||DC-input||4-pin DIN power adaptor|
|S14||Power Switch||Slide switch for power input|
The target FPGA device this kit is designed to work with is the Intel® Cyclone® 10 GX 10CX220YF780E5G FPGA. It is the device with the fastest speed, largest resource and biggest package in the Intel® Cyclone® 10 GX FPGA series.
|Logic Elements (LE)||220K|
|Memory - M20K||11,740 Kb|
|Memory - MLAB||1,690|
|Variable precision DSP block||192|
|18 x 19 Multiplier||384|
|Hard Floating-point Arithmetic||Yes|
|PLL (Fractional Synthesis)||4|
|12.5 Gbps Transceiver||12|
|PCIe Hard IP Block||1|
|Hard Memory Interfaces||2|
|Package||F780 (29 mm x 29 mm)|
The table below presents a summary of the Intel® Cyclone® 10 GX FPGA I/O resource allocation. I/O Direction is with respect to the FPGA.
|Bank Number||Function||I/O Type||I/O Count||Description|
|1C||USB_REFCLK||2||125 MHz (adjustable) , AC|
|1C||FMC_GBTCLK_M2C||LVDS input||2||User-defined from FMC, AC|
|1D||SFP_REFCLK||LVDS input||2||644.53125 MHz (adjustable), AC|
|1D||PCIE_REFCLK||LVDS input||2||100 MHz from PCIe, DC|
|1C/1D||PCIE_TX [0:3]||CML output||8(4p)||PCIe® Gen2 Transmit|
|1C/1D||PCIE_RX [0:3]||CML/LVDS input||8(4p)||PCIe® Gen2 Receive|
|1D||SFP+_TX [0:1]||CML output||4(2p)||SFP+ Transmit|
|1D||SFP+_RX [0:1]||CML / LVDS input||4(2p)||SFP+ Receive|
|1D||USB31_TX||CML output||2(1p)||USB3.1 Trasnsmit|
|1D||USB31_RX||CML/LVDS input||2(1p)||USB3.1 Receive|
|1C/1D||FMC_DP_C2M [0:4]||CML output||10(5p)||FMC Transmit|
|1C/1D||FMC_DP_M2C [0:4]||CML/LVDS input||10(5p)||FMC Receive|
|Global FPGA Clocks|
|2A||M10_USB_CLK||1.8 V CMOS input||1||30/48 MHz from U2 (MAX10)|
|2A||C10_REFCLK1||LVDS input||2||125 MHz (adjustable)|
|2L||C10_CLK50M||1.8 V CMOS input||1||50 MHz OSC, free running|
|2L||C10_REFCLK2||LVCMOS input||2||100 MHz (adjustable)|
|2J||REFCLK_EMIF||LVDS input||2||21.186 MHz (adjustable)|
|Global FPGA Reset|
|2A||FPGA_RESETn||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|CSS||C10_TCK||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|CSS||C10_TMS||1.8V CMOS input||1||From U2 ( Intel® MAX® 10)|
|CSS||C10_TDI||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|CSS||C10_TDO||1.8 V CMOS input||1||To U2 ( Intel® MAX® 10)|
|2A||C10_CLKUSR||1.8 V CMOS input||1||100 MHz, for calibration|
|CSS||C10_MSEL[0:1]||1.8 V CMOS input||2||From DIP Switch S1|
|CSS||C10_nSTATUS||1.8 V CMOS output||1||To U2/U3 ( Intel® MAX® 10)|
|CSS||C10_CONF_DONE||1.8 V CMOS output||1||To U2/U3 ( Intel® MAX® 10)|
|CSS||C10_nCONFIG||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|CSS||C10_CS0n||1.8 V CMOS output||1||To U4 (EPCQ-L)|
|CSS||C10_AS_D [0:3]||1.8 V CMOS inout||4||To U4 (EPCQ-L)|
|CSS||C10_DCLK||1.8 V CMOS inout||1||
To U4 (EPCQ-L) for ASx4
From U3 ( Intel® MAX® 10)for FPPx16
|2A||FPP [0:15]||1.8 V CMOS input||16||From U3 ( Intel® MAX® 10)|
|2A||CVP_CONFDONE||1.8 V CMOS output||1||To U2 ( Intel® MAX® 10)|
|UBII Side Bus|
|2A||M10_USB_DATA [0:7]||1.8 V CMOS input||8||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_ADDR [0:1]||1.8 V CMOS input||2||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_RDn||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_WRn||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_RESETn||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_FULL||1.8 V CMOS output||1||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_EMPTY||1.8 V CMOS output||1||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_Oen||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_SCL||1.8 V CMOS input||1||From U2 ( Intel® MAX® 10)|
|2A||M10_USB_SDA||1.8 V CMOS inout||1||From U2 ( Intel® MAX® 10)|
|2J||DDR3_A [0:14]||1.5 V SSTL output||15||To U12/U13/U14 DDR3|
|2J||DDR3_BA [0:2]||1.5 V SSTL output||3||To U12/U13/U14 DDR3|
|2J||DDR3_RASn||1.5 V SSTL output||1||To U12/U13/U14 DDR3|
|2J||DDR3_CASn||1.5 V SSTL output||1||To U12/U13/U14 DDR3|
|2J||DDR3_WEn||1.5 V SSTL output||1||To U12/U13/U14 DDR3|
|2J||DDR3_CK||1.5 V SSTL output||2||To U12/U13/U14 DDR3|
|2J||DDR3_CKE [0:1]||1.5 V SSTL output||2||To U12/U13/U14 DDR3|
|2J||DDR3_ODT [0:1]||1.5 V SSTL output||2||To U12/U13/U14 DDR3|
|2J||DDR3_CS [0:1]||1.5 V SSTL output||2||To U12/U13/U14 DDR3|
|2J||DDR3_RSTn||1.5 V CMOS output||1||To U12/U13/U14 DDR3|
|2J/2K||DDR3_D [0:39]||1.5 V SSTL inout||40||To U12/U13/U14 DDR3|
|2J/2K||DDR3_DQS [0:4]||1.5 V SSTL inout||10||To U12/U13/U14 DDR3|
|FMC LVDS GPIO|
|3A/3B||FMC_LA_TX [0:16]||Vadj CMOS inout||34||To J7 (FMC), DC|
|3A/3B||FMC_LA_RX [0:14]||Vadj CMOS inout||30||To J7 (FMC), DC|
|3A/3B||FMC_LA_CC [0:1]||Vadj CMOS input||4||From J7 (FMC), DC|
|3A/3B||FMCA_CLK_M2C [0:1]||Vadj CMOS input||4||From J7 (FMC), DC|
|3B||FMC_PRSN_1V8||Vadj CMOS input||1||From J7 (FMC)|
|3A||FMC_SCL||Vadj CMOS output||1||To J7 (FMC)|
|3A||FMC_SDA||Vadj CMOS inout||1||To J7 (FMC)|
|2A||SGMII_TXP/N||LVDS output||2||To U33 (88E1111 PHY), AC|
|2A||SGMII_TXP/N||LVDS input||2||To U33 (88E1111 PHY), AC|
|2L||ETH_MDC_C10||1.8 V CMOS output||1||To U33 (88E1111 PHY)|
|2L||ETH_MDIO_C10||1.8 V CMOS inout||1||To U33 (88E1111 PHY), AC|
|2L||ETH_INTn_C10||1.8 V CMOS input||1||To U33 (88E1111 PHY), AC|
|2L||ETH_RESETn_C10||1.8 V CMOS output||1||To U33 (88E1111 PHY), AC|
|2L||SFP_SCL_0||1.8 V CMOS output||1||To J5 (SFP+ 0)|
|2L||SFP_SDA_0||1.8 V CMOS inout||1||To J5 (SFP+ 0)|
|2L||SFP_INT_0||1.8 V CMOS input||1||To J5 (SFP+ 0)|
|2L||SFP_SCL_1||1.8 V CMOS output||1||To J6 (SFP+ 1)|
|2L||SFP_SDA_1||1.8 V CMOS inout||1||To J6 (SFP+ 1)|
|2L||SFP_INT_1||1.8 V CMOS input||1||To J6 (SFP+ 1)|
|2L||PCIE_WAKEn||1.8 V CMOS input||1||To golden finger, reserved|
|2L||PCIE_SMBCLK||1.8 V CMOS output||1||To golden finger|
|2L||PCIE_SMBDAT||1.8 V CMOS inout||1||To golden finger|
|2A||PCIE_PERSTn||1.8 V CMOS input||1||To golden finger|
|ULPI (USB 2.0)|
|2L||USB_D [0:7]||1.8 V CMOS inout||8||To U32 (USB Transceiver)|
|2L||USB_NXT||1.8 V CMOS input||1||To U32 (USB Transceiver)|
|2L||USB_DIR||1.8 V CMOS input||1||To U32 (USB Transceiver)|
|2L||USB_STP||1.8 V CMOS output||1||To U32 (USB Transceiver)|
|2L||USB_CLK||1.8 V CMOS output||1||60 MHz, REFCLK for ULPI|
|2L||USB_RESETn||1.8 V CMOS output||1||To U32 (USB Transceiver)|
|2L||USB_SCL||1.8 V CMOS output||1||To U26 (USB3.1 Transceiver Switch)|
|2L||USB_SDA||1.8 V CMOS inout||1||To U26 (USB3.1 Transceiver Switch)|
|2L||USB_PWEN||1.8 V CMOS output||1||To U25 (USB3.1 Transceiver Switch)|
|2L||USB_SW_INTn_1.8V||1.8 V CMOS input||1||To U26 (USB3.1 Transceiver Switch)|
|2L||USB_ID_1.8V||1.8 V CMOS input||1||To U26 (USB3.1 Transceiver Switch)|
|2L||C10_QSPI_CSn||1.8 V CMOS output||1||To U58 (QSPI Flash)|
|2L||C10_QSPI_RESETn||1.8 V CMOS output||1||To U58 (QSPI Flash)|
|2L||C10_QSPI_CLK||1.8 V CMOS output||1||To U58 (QSPI Flash)|
|2L||C10_QSPI_D [0:3]||1.8 V CMOS inout||4||To U58 (QSPI Flash)|
- Internally stored dual configuration flash
- User flash memory
- Instant on support
- Integrated analog-to-digital converter (ADC)
- Single-chip Nios II soft core processor support
Intel® MAX® 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
|Technology||55 nm TSMC Embedded Flash (Flash + SRAM) process technology|
|Internal memory blocks||
|User flash memory (UFM)||
|Embedded multiplier blocks||
|Internal oscillator||Built-in internal ring oscillator|
|General-purpose I/Os (GPIOs)||
|External memory interface (EMIF)|| Supports up to 600 Mbps external
|Flexible power supply schemes||
The JTAG topology of the board is shown in the figure below. An on-board USB Blaster is implemented with the Intel® MAX® 10. It is in the form of a micro-USB type-B connector (J9).
The system Intel® MAX® 10 device itself can be configured through on-board USB port or an external USB-Blaster II header. the 2x5 header for Intel® MAX® 10 is not mounted by default.
A secondary Intel® MAX® 10 device is used for PFL configuration mode. This CFG Intel® MAX® 10 is configured with on-board USB port.
The Intel® Cyclone® 10 GX FPGA device is configured with on-board USB port or an external USB-Blaster II header.
The FMC interface also has a JTAG interface. The FMC JTAG can also be included into the JTAG chain.
The Intel® Cyclone® 10 GX device JTAG and FMC JTAG can be put included or isolated from the JTAG chain by setting a DIP switch S5.
|S5.1||FMC_JTAGEN||ON - Disable JTAG|
|S5.2||C10_JTAGEN||ON - Disable JTAG|
The Intel® Cyclone® 10 GX FPGA device can be configured using different modes. Mode selection can be done using DIP switch S1.
|Configuration Scheme||VCCPGM (V)||Power-On Reset Delay||Valid MSEL [2:0]|
|JTAG-based Configuration||-----||------||Use any valid MSEL pin settings given below|
|AS (x1 and x4)||1.8||Fast||010|
|PS and FPP (x8, x16, x32)||1.2 / 1.5 / 1.8||Fast||000|
MSEL2 is tied to GND
ON - '0'
The Intel® Cyclone® 10 GX FPGA device is configured with two modes: ASx4 or FPP x16. The AS x4 mode uses an EPCQ-L 1024 to store the image. A dedicated Intel® MAX® 10 device is used to implement PFL. It interfaces with two pieces of x16 parallel NOR flash devices to get a x32 bus width. The highest density is 2 Gb. The flash interface works at 3.3 V and various NOR flashes from different vendors can be used with this board.
Micron MT28EW01GABA1LPC-0SITES is installed in manufacturing by default. 2 Gb is provided with the board.
For the Intel® Cyclone® 10 GX FPGA device, the image size is less than 85 Mb. Multiple images can be stored and selected by the user. The image to be used can be selected with a group of Push Buttons and LEDs.
- Cycling images by pushing button S7
- CFG Intel® MAX® 10 device displays current number to be used with LEDs D16-D18
- Initiate the reconfiguration by pushing button S12
|Switch / LED||Signal||Note|
|D16||PGM_LED0||PGM_LED [2:0] indicates the program to be used|
A group of Side Bus signals are defined between Intel® MAX® 10 and Intel® Cyclone® 10 GX FPGA device to provide a higher speed access through on-board USB-Blaster. This interface is reserved in harwdare.
The Power Switch S14 is at the edge of the card. When the switch stub is at higher position (marked 'OFF'), the power is OFF.
The DIP switches are on the bottom side of the board, close to the upper edge.
|Board Reference||Switch||Signal Name||Default Value||Function|
|S9||S9.1||USER_DIP0||1||User available Digital Input 0|
|S9.2||USER_DIP1||1||User available Digital Input 1|
|S15||S15.1||USER_DIP2||1||User available Digital Input 2|
|S15.2||USER_DIP3||1||User available Digital Input 3|
|S6||S6.1||CFG_M10_PGM0||1||Reserved, No Function|
|S1||S1.1||C10_MSEL0||1||Intel® Cyclone® 10 GX MSEL|
Input selection for clock generator chip, the Si5332 on this board
[INSEL1, INSEL0] values:
01 - internal oscillator
10- external reference input from SMB
Set to 01 by default
Set the input source of Si53307
0: Use CLKIN0
1: Use CLKIN1
Fixed to '0'
Enable the output of Si570 (Y2)
0: Output disabled
1: Output enabled
Fixed to '1'
Enable FMC Card JTAG
0: Isolate FMC card JTAG from the chain
1: Add FMC Card JTAG into the chain
Enable Intel® Cyclone® 10 GX FPGA JTAG
0: Isolate FPGA JTAG from the chain
1: Add FPGA JTAG into the chain
The push buttons are located on the upper right corner of the board.
|Board Reference||Signal Name||Function|
|S11||USER_PB2||User available Pushbutton 2|
|S10||USER_PB1||User available Pushbutton 1|
|S8||USER_PB0||User available Pushbutton 0|
|S7||PGM_SEL||PFL Image selection. Use this pushbutton to rotate through three images.|
|S12||SYS_CONFIG_PB||Trigger reconfiguration to Intel® Cyclone® 10 GX FPGA. The image used for configuration is selected with PGM_SEL button and indicated by PGM_NUM LEDs|
|S13||C10_RESETn_PB||Trigger logic reset to Intel® Cyclone® 10 GX FPGA logic. The state of the configured logic is reset, the configuration remains unchanged.|
The LEDs are on the top side of the board at the upper right corner.
|Board Reference||Signal Name||Colour||Function|
|D16||PGM_LED0||Green||Image 0 is loaded in FPP mode|
|D17||PGM_LED1||Green||Image 1 is loaded in FPP mode|
|D18||PGM_LED2||Green||Image 2 is loaded in FPP mode|
|D14||LOAD_LED||Green||Indicates image is loading|
|D15||CFGDONE_LED||Green||Indicates image loading succeeded|
|D13||ERR_LED||Red||Indicates image loading failed|
|D22||USER_LED3||Green||'0' to light, output from FPGA|
|D19||USER_LED0||Green||'0' to light, output from FPGA|
|D20||USER_LED1||Green||'0' to light, output from FPGA|
|D21||USER_LED2||Green||'0' to light, output from FPGA|
|D23||POK_LED||Green||Indicates power is OK|
The Intel® Cyclone® 10 GX FPGA local clocks are generated with Si570 + Si53307 + Si5332.
Si570 is a programmable oscillator. It is configurable with an I2C interface at address 7'b110_0110. Si53307 is a clock buffer. With Si570 + Si53307, a high frequency reference clock at frequency up to 725 MHz is available for Intel® Cyclone® 10 GX FPGA Transceiver. Other clocks are generated with an programmable clock generator Si5332 at I2C address 7'b110_1010.
Features of Si5332
- Output frequency Range: 5 MHz to 312.5 MHz differential
- Input frequency Range: 10 MHz to 250 MHz differential, 16 MHz to 30 MHz external crystal
- Embedded 50 MHz crystal option for 8 or 12 port devices
- MultiSynth technology enables any frequency synthesis on any output up to 250 MHz
- Highly configurable output path featuring a cross-point multiplexer
- Up to three independent fractional synthesis output paths
- Up to five independent integer dividers
- The Input Reference Clock
- Low Phase Jitter: 400 fs rms max
- Programmable spread spectrum
- 1.8 V, 2.5 V, 3.3 V core VDD
- 1.8 V, 2.5 V, 3.3 V differential output
A local free running 100 MHz oscillator is used to generate the reference clock for calibration. This clock is also used by ASx4 configuration. A free running 50 MHz oscillator is used to generate a reference clock for FPGA core.
The Intel® MAX® 10 works with free running 50 MHz oscillator. Adjusting the variable clocks does not affect the working of the Intel® MAX® 10 device.
The Intel® Cyclone® 10 GX FPGA device supports DDR3 memory up to 933 MHz. On this development kit, a DDR3 x40 at 933 MHz is implemented with DDR3 devices. The EMIF uses continuous banks in the same column. To achieve 933 MHz speed, EMIF uses bank 2J and 2K to support 40-bit width at 933 MHz. The signal definition conforms to the EMIF constraints.
Besides the flash memories used by the configuration modules, a user accessible QSPI Flash device is provided for non-volatile data storage. The device is 256 Mb with 4-bit data width.
- PCIe® golden finger from PCIe® system
- ATX 2 x 4 or external AC/DC adaptor.
|Power Group||Power Rail||Generated From (V)||Maximum Current (A)||Enpirion® Part|
|0||3.3 V for Intel® MAX® 10||12||0.65||ER3110|
|5 V for EM2130||12||0.20||ER3105|
|2.5 V for clock||3.3||0.22||EY1501|
|2.5 V for GigE||3.3||0.40||EP5348|
|1 V for GigE||3.3||0.30||EP5348|
|5 V for USB3.1||12||1.50||ER2120|
The Intel® Cyclone® 10 GX FPGA device has 12 channels of transceivers that work at 12.5 Gbps. The transceivers are organized in two banks, each bank has six channels.
|Channel Number (Bank 1C)||Function (Bank 1C)||Channel Number (Bank 1D)||Function (Bank 1D)|
|0||FMC_DP ||0||PCIe |
|1||FMC_DP ||1||PCIe |
|2||FMC_DP ||2||FMC_DP |
|3||FMC_DP ||3||SFP+ 1|
|4||PCIe ||4||SFP+ 0|
The PCIe® x4 Gen2 Hard IP with CvP is implemented in this development kit. The position of the PCIe® channels is fixed by the hard IP. This development kit is a PCIe® add-in card. The PCIe® interface is configured to End-Point.
- Transceivers, x4, up to 5 Gbps
- PCIE_REFCLKp/n, 100 MHz from PCIe® system
- PCIE_SMBUS, 3.3V level-translated to 1.8V with U18
- PCIE_PERSTn, 3.3V level-translated to 1.8V with U17
- PCIE_WAKEn, 3.3V level-translated to 1.8V with U17, reserved
- R506 installed, x1 mode
- R507 installed, x4 mode, this is the default mode
- +12 V, +/- 8 %, up to 75 W, is used as power of the board
- +3.3 V, +/- 9 %, up to 10 W, is not used on this board
- +3.3 Vaux, +/- 9 %, 375 mA max, is not used since wakeup is not supported
Two SFP+ connectors (J5, J6) are provided on the PCIe® bracket. Each connector supports a 10 GE SFP+ hot pluggable module.
- Transceivers, x1 for each SFP+, up to 12.5 Gbps
- SMBUS (I2C), 3.3V for SFP+ and I/O expander, level-translated 10 1.8V with U22/U23
- IRQ of I/O expander, 3.3V level-translated to 1.8V with U19
Each SFP+ module has six status/control signals and two LEDs. The FPGA device does not have enough I/O pins for these signals, hence an I/O expander is used to implement these I/Os for each SFP+ connector. The I2C I/O expander is on the same I2C bus as the SFP+ module, and the I2C bus of two SFP+ modules are independent of each other.
The I/O expander used is TI TCA9534PWR. U20 is for SFP+ 0, with I2C address 7'b010_0000. U21 is for SFP+, with I2C address 7'b010_0000.
The I/O expander has 8 I/Os. The definition of the I/Os is shown in the table below. The device is controlled with I2C bus.
|I/O Number||Signal||I/O Type||Function|
|P0||SFP_RLED||Output||Red LED, indicates LOS/ERR, "0" - ON|
|P1||SFP_GLED||Output||Green LED, indicates Link, "0" - ON|
|P2||SFP_TXDIS||Output||Tx_Disable, Pulled up, Transmitter is turned off if high|
|P3||SFP_TFLT||Input||Tx_Fault, Pulled up, indicates fault when high|
|P4||SFP_RS1||Output||Rate Select, Pulled up with 1K resistor|
|P5||SFP_RLOS||Input||Rx_LOS, Pulled up, indicates LOS when high|
|P6||SFP_RS0||Output||Rate Select, Pulled up with 1K resistor|
|P7||SFP_PRSN||Input||Mod_ABS, Pulled up, module in place when low|
The I/Os of TCA9534 is in high impedance input mode upon power up. Hence, the module is placed in TX_Disable mode and the LEDs are off. The status changes on the I/Os are reported with an IRQ to the FPGA. Each I/O expander has its own dedicated IRQ signal.
A USB3.1 Type-C interface (J8) is provided on the PCIe® bracket. The interface supports SuperSpeed up to 10 Gbps as well as the backward compatible support of USB2.0.
The Type-C connector provides any orientation insertion of the cable. To support this feature, a Texas Instruments DRP port Controller and SuperSpeed 2:1 MUX HD3SS3220 is used. The port is configured in DRP mode. The controller detects the orientation of the plugged cable and multiplexes the transceiver of the FPGA to two SuperSpeed interfaces. It also determines if the port is an Upstream Facing Port (UFP) or a Downstream Facing Port (DFP). It controls the power switch to feed the power to cable when in DFP mode. HD3SS3220 is controlled by the FPGA through a dedicated I2C bus.
Parameters of USB3.1
- I2C address is 7'b110_0111 by default. It can be changed to 7'b100_0111 by installing R199 and removing R198
- Port mode is Dual Role Port (DRP) by default. It can be chnaged to DFP if R177 is installed, or UFP if R178 is installed.
- Current Advertisement is 1.5A
- EQ for channel 1: 5.5 dB
- EQ for channel 2: 5.5 dB
- VOD Gain: 0 for both channels with linear range 1200 mV.
The resistors are set in pull down mode on the board. Other configurations are available by changing the pulling resistors. EQ configurations with pin level "1" are not available.
The power of USB VBUS is controlled with a Texas Instruments power switch TPS25910. The voltage is 5 V and the maximum current is 1.5 A. The power control pin to the TPS25910 is connected to the USB_ID output of HD3SS3220. The power is applied to VBUS only when the port is in DFP mode. The power application can be controlled by the FPGA too. The USB_PWEN signal is active high because of the NMOS inverter.
USB_ID pin on HD3SS3220 indicates the port is linked as a power source (DFP), or dual-role (DRP) acting as source (DFP). USB_ID is connected to the FPGA as well as TPS25910 and USB3320.
Backward support for USB2.0 is implemented with Microchip's USB3320 USB PHY. It interfaces with the FPGA through ULPI interface. The reference clock mode for ULPI is FPGA clock output to USB3320.
- 12G SDI: Semtech RDK-12GSRD-ALTRA00 Evaluation Board
- 8G DisplayPort: Bitec FMC DisplaPort Daughter Card
- 6G HDMI 2.0: Bitec FMC HDMI Daughter Card
|Intel® Cyclone® 10 GX FPGA Development Kit||SDI||DisplayPort||HDMI|
|Signal||V57.1 Name||Signal Name||Pin Number||SDI FMC Signal Name||DisplayPort FMC Signal Name||HDMI FMC Signal Name|
A copper Ethernet connector (RJ1) is provided on the PCIe bracket. This interface is implemented with Marvell 88E1111 10/100/1000Base-T Ethernet PHY.
|Hardware Configuration Pins||Connection||Bits||Bit ||Bit ||Bit |
|Config0||GND||000||PHYADR [2:0] = 000|
|Config1||GND||000||ENA_PAUSE = 0||PHYADR [4:3] = 00|
|Config2||VDDO||111||ANEG [3:1] = 111|
|Config3||GND||000||ANEG  = 0||ENA_XC = 0||DIS_125 = 0|
|Config4||LED_1000||100||HWCFG_MODE [2:0] = 100|
|Config5||LED_10||110||DIS_FC = 1||DIS_SLEEP = 1||HWCFG_MODE  = 0|
|Config6||LED_RX||010||SEL_TWSI = 0||INT_POL = 1||75/50 OHM = 0|
- Select MDC/MDIO interface. PHY address is 5'b00000.
- INTn signal is active low
- 50 Ohm termination for SGMII
- Disable fiber/copper auto selection
- Hardware Configuration mode is "SGMII without Clock with SGMII Auto-Neg to copper"
- Energy detect is disabled
- Diasble crsoover
- PAUSE is disabled
The registers of the Marvell 88E1111 device can be changed with MDC/MDIO. The MDC/MDIO is connected to the FPGA device through a level translator.
The power and various peripherals are managed by I2C/PMBUS. The topology of the I2C bus is shown in the figure below.
The Intel® Cyclone® 10 GX FPGA Development Kit includes a design example and an application called the Board Test System (BTS) to test the functionality of this board. The BTS provides an easy-to-use interface to alter functional settings and observe results. You can use the BTS to test board components, modify functional parameters, observe performance and measure power usage.
While using the BTS, you reconfigure the FPGA several times with test designs specific to the functionality that you are testing. The BTS is also useful as a reference for designing systems. The BTS communicates over the JTAG bus to a test design running in the Intel® Cyclone® 10 GX GX FPGA device.
The figure below shows the Graphical User Interface (GUI) for a board that is in factory configuration.
Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application. The Configure Menu identifies the appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears that allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.
The BTS communicates over the JTAG bus to a test design running in the FPGA. The BTS and Power Monitor share the JTAG bus with other applications like the Nios® II debugger and the Signal Tap II Embedded Logic Analyzer. Because the BTS is designed based on the Intel® Quartus® Prime software, be sure to close other applications before you use the BTS.
The BTS relies on the Intel® Quartus® Prime software's specific library. Before running the BTS, open the Intel® Quartus® Prime software to automatically set the environment variable $QUARTUS_ROOTDIR. The BTS uses this environment variable to locate the Intel® Quartus® Prime library. The version of Intel® Quartus® Prime software set in the QUARTUS_ROOTDIR environment variable should be newer than version 14.1. For example, the Development Kit Installer version 15.1 requires that the Intel® Quartus® Prime software 14.1 or later version to be installed.
Also, to ensure that the FPGA is configured successfully, you should install the latest Intel® Quartus® Prime software that can support the silicon on the development kit. For this board, we recommend you install Intel® Quartus® Prime version 220.127.116.11.
Please refer to the README.txt file for more information in the examples\board_test_system directory.
Before you begin
- Connect the USB cable to your PC and the board.
- Check whether the development board swicthes and jumpers are set according to your preferences.
- Set the load selector switch (S1) to (OFF OFF) for standard ASx4 mode. The development kit ships with the EPCQ Flash device preprogrammed with a default Simple Socket Server Example.
- Turn on the power to the board. The board loads the design stored in the EPCQ flash memory into the FPGA.
To run the BTS
- Navigate to the <package dir>\examples\board_test_system directory and run the BoardTestSystem.exe application.
- A GUI appears, displaying the application tab corresponding to the design running in the FPGA. If the design loaded in the FPGA is not supported by the BTS GUI, you will receive a message prompting you to configure your board with a valid BTS design. Refer to the Configure Menu on configuring your board.
This section describes each control in the BTS.
Use the Configure Menu to select the design you want to use. Each design example tests different board features. Select a design from this menu and the corresponding tabs become active for testing.
- On the Configure menu, click the configure command that corresponds to the functionality you wish to test.
- In the dialog box that appears, click Configure to download the corresponding design to the FPGA.
- When configuration finishes, the design begins running in the FPGA. The corresponding GUI application tabs that interface with the design are now enabled.
If you use the Intel® Quartus® Prime Programmer for configuration, rather than the BTS GUI, you may need to restart the GUI.
The System Info tab shows the board's current configuration. The tab displays the contents of the Intel® MAX® 10 registers, the JTAG chain, the board's MAC address, and other details stored on the board.
The following sections describe the controls of the System info tab
- Board Name: Indicates the official name of the board given by BTS
- Board P/N: Indicates thr part number of the board
- Serial Number: Indicates the serial number of the board
- Board Revision: Indicates the revision of the board
- MAC Address: Indicates MAC Address of the board
System MAX Control
MAX Ver: Indicates the vesion of Intel® MAX® 10 code currently running on the board.
The Intel® MAX® 10 code resides in the <package dir>\examples\max10 directory. Newer revisions of this code may be available on the Intel® Cyclone® 10 GX FPGA Development kit link on the Altera website.
The Intel® MAX® 10 register control allows you to view and change the current Intel® MAX® 10 register values as described in the table below. Change to the register values with the GUI take effect immediately.
|MAX 10 Register Values||Description|
|Configure||Resets the system and reloads the FPGA with a design from the CFI flash memory based on the other Intel® MAX® 10 register values. It works only in FPP mode.|
|PSO||Sets the Intel® MAX® 10 PSO register.|
|PSR||Sets the Intel® MAX® 10 PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corresponds to the page of flash memory to load during the FPGA configuration.|
|PSS||Displays the Intel® MAX® 10 PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.|
The JTAG chain shows all the devices currently in the JTAG chain.
The GPIO tab allows you to interact with all the general purpose user I/O components on your board. You can read DIP switch settings, turn LEDs on or off and detect push button presses.
The following sections describe the controls on the GPIO tab.
User DIP Switch
The read-only User DIP Switch control displays the current positions of the switches in the user DIP switch bank (SW1). Change the switches on the board to see the graphical display change.
The User LEDs control displays the current state of the user LEDS. Toggle the LED buttons to turn the board LEDs on or off.
Read only control displays the current state of the board user push buttons. Press a push button on the board to see the graphical display change accordingly.
Qsys Memory Map
The Qsys memory map control shows the memory map of the bts_config.sof design running on your board.
The EPCQ tab allows you to read and write EPCQ flash memory on your board. The memory table displays the address 0 contents by default after you configure the FPGA.
The following sections describe the controls on the Flash tab
Reads the flash memory on your board. To see the flash memory contents, type a starting address in the text box and click Read. Values starting at the specified address in the table.
Writes the flash memory on your board. To update the flash memory contents, change values in the table then press the Enter key and click Write. The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.
Starts a random data pattern test to flash memory, limited to the 512K test system scratch page.
Starts an incrementing data pattern test to flash memory, limited to the 512K test system scratch page.
Erases flash memory of the current sector.
Flash Memory Map
Displays the flash memory map for the development board.
This tab allows you to perform loopback tests on the PCIe® and SFP+ ports.
- PLL lock: Shows the PLL locked or unlocked state.
- Pattern sync: Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.
- Details: Shows the PLL lock, pattern sync status and number of errors for a single channel.
- Serial Loopback: Routes signals between the transmitter and the receiver.
- VOD: Specifies the voltage output differential of the transmitter buffer.
- Pre-emphasis tap:
- 1st pre: Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
- 2nd pre: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
- 1st post: Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
- 2nd post: Specifies the amount of pre-emphasis on the second post tap of the transmitter buffer.
- Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage mode.
- DC gain: Specifies the DC gain setting for the receiver equalizer in four stage mode.
- VGA: Specifies the VGA gain value.
- PRBS 7: Selects pseudo-random 7-bit sequences.
- PRBS 15: Selects pseudo-random 15-bit sequences.
- PRBS 23: Selects pseudo-random 23-bit sequences.
- PRBS 31: Selects pseudo-random 31-bit sequences.
- high_freq: Selects highest frequency divide-by-2 data pattern 10101010.
- low_freq: Selects lowest frequency divide-by-33 data pattern.
- Detected errors: Displays the number of data errors detected in the hardware.
- Inserted errors: Displays the number of errors inserted into the transmit data stream.
- Insert: Inserts a one-word error into the transmit data stream each time you click the button. Insert is only enabled during transaction performance analysis.
- Clear: Resets the Detected errors and Inserted errors counters to zeroes.
Start: Initiates the selected ports transaction performance
analysis. Note: Always click Clear before Start.
- Stop: Terminates transaction performance analysis.
- TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
This tab allows you to perform loopback tests on the FMC port.
The following sections describe controls in the FMC tab.
- PLL Lock: Shows the PLL locked or unlocked state.
- Pattern Sync: Shows the pattern synced or not synced state. The pattern is considered synced when the start of he data data sequence is detected.
- Details: Shows the PLL lock, pattern sync status and number of errors per channel.
- Serial Loopback: Routes signals between the transmitter and receiver.
- VOD: Specifies the voltage output differential of the transmitter buffer.
- Pre-emphasis tap:
- 1st pre - Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
- 2nd pre - Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
- 1st post - Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
- 2nd post - Specifies the amount of pre-emphasis on the second post tap of the transmitter buffer.
- Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage mode.
- DC gain: Specifies the DC gain setting for the receiver equalizer in four stage mode.
- VGA: Specifies the VGA gain value.
- PRBS 7- Selects pseudo-random 7-bit sequences
- PRBS 15- Selects pseudo-random 15-bit sequences
- PRBS 23- Selects pseudo-random 23-bit sequences
- PRBS 31-Selects pseudo-random 31-bit sequences
- high_freq - Selects highest frequency divide-by-2 data pattern 10101010
- low_freq - Selects lowest frequency divide-by-33 data pattern
- Detected errors - Displays the number of data errors detected in the hardware.
- Inserted errors - Displays the number of errors inserted into the transmit data stream.
- Insert Error - Inserts a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
- Clear - Resets the Detected error and Inserted error counters to zeroes.
Stop - Terminates transaction performance analysis.
TX and RX performance bars - Shows the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
This tab allows you to read and write DDR3 memory on your board.
The following sections describe the controls on the DDR3 tab.
Initiates DDR3 memory transaction performance analysis.
Terminates transaction performance analysis.
- Write, Read and Total performance bars: Shows the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
- Write (MBps), Read(MBps) and Total(MBps): Show the number of bytes of data analayzed per second.
- Detected: Displays the number of data errors detected in the hardware.
- Inserted: Displays the number of errors inserted into the transaction stream.
- Insert: Inserts a one-word error into the transaction stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
- Clear: Resets the Detected errors and Inserted errors counters to zeroes.
Address Range (Bytes)
Determines the number of bytes to use in each iteration of reads and writes.
The Power Monitor measures and reports current power information and communicates with the Intel® MAX® 10 device on the board through the JTAG bus. A power monitor circuit attached to the Intel® MAX® 10 device allows you to measure the power that the FPGA is consuming.
To start the application, click the Power Monitor icon in the BTS. You can also run the Power Monitor as a stand-alone application. The PowerMonitor.exe resides in the <package dir>\examples\board_test_system directory.
The controls on the Power Monitor are described below.
Displays the mA power consumption of your board over time. The green line indicates the current value. The red line indicates the maximum value read since the last reset. The yellow line indicates the minimum value read since the last reset.
It also displays root mean square (RMS) current, maximum and minimum numerical power readings in mA.
Displays real time values of power rails. It refreshes about every 10 seconds.
When you click some rail, the power rail will show on the Graph Chart.
Speed Adjustment: Specifies how often to refresh the graph.
Date Record: Record real time voltage, current and power values, and save to a log file.
Clears the graph, resets the minimum and maximum values and restarts the Power Monitor.
Displays the temperature of the FPGA and the development kit.
The Clock Controller application sets the Si5332 programmable oscillators to any frequency between 5 MHz and 312.5 MHz differential.
The Clock Controller application sets the Si570 programmable oscillators to any frequency between 10 MHz and 725 MHz.
The Clock Control communicates with the Intel® MAX® 10 on the board through the JTAG bus. The programmable oscillator are connected to the Intel® MAX® 10 device through a 2-wire serial bus.
Serial Port Registers
Shows the current values from the Si570 registers for frequency configuration.
Target Frequency (MHz)
Allows you to specify the frequency of the clock. Legal values are between 10 MHz and 725 MHz with eight digits of precision to the right of the decimal point. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target Frequency control works in conjunction with the Set control.
Shows the calculated internal fixed-frequency crystal based on the serial port register values.
Sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board.
Sets the programmable oscillator frequency for the selected clock to the value in the Target Frequency control for the programmable oscillators. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this period. Altera® recommends resetting the FPGA logic after changing frequencies.
Si5332 tab displays the same GUI controls for each clock generators. The Si5332 is a high-performance, low-jitter clock generator capabale of synthesizing five independent banks for user-programmable clock frequencies up to 312.5 MHz.
The controls of the clock controller are described below:
Displays the generating signal value of the voltage-controlled oscillator.
Allows you to specify the frequency of the clock MHz.
Display the divider mode and value currently being used on this board.
Allows you to disable a single output.
Reads the current frequency setting for the oscillator.
Sets the programmable oscillator frequency for the selected clock to the value in OUT0, OUT1, OUT4, OUT6 and OUT7 controls for the Si5332. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this period. Altera® recommends resetting the FPGA logic after changing frequencies.
Import register map file generated from Silicon Laboratories ClockBuilder Desktop.
ENGINEERING DEVELOPMENT PRODUCT - NOT FOR RESALE OR LEASE
This development kit is intended for laboratory development and engineering use only.
- Product developers and system engineers to evaluate electronic components, circuits, or software associated with the development kit to determine whether to incorporate such items in a finished product.
- Software developers to write software applications for use with the end product.
This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required Federal Communications Commission (FCC) equipment authorizations are first obtained.
Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under Part 15, Part 18 or Part 95 of the United States Code of Federal Regulations (CFR) Title 47, the operator of the kit must operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47.
Safety Assessment and CE mark requirements have been completed, however, other certifications that may be required for installation and operation in your region have not been obtained.
Power Supply Hazardous Voltage
AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply.
Power Connect and Disconnect
The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system. The socket outlet must be installed near the equipment and must be readily accessible.
System Grounding (Earthing)
To avoid shock, you must ensure that the power cord is connected to a properly wired and grounded receptacle. Ensure that any equipment to which this product will be attached is also connected to properly wired and grounded receptacles.
Power Cord Requirements
The connector that plugs into the wall outlet must be a grounding-type male plug designed for use in your region. It must have marks showing certification by an agency in your region. The connector that plugs into the AC receptacle on the power supply must be an IEC 320, sheet C13, female connector. If the power cord supplied with the system does not meet requirements for use in your region, discard the cord and do not use it with adapters.
Do not connect/disconnect any cables or perform installation/maintenance of this product during an electrical storm.
Risk of Fire
To reduce the risk of fire, keep all flammable materials a safe distance away from the boards and power supply. You must configure the development kit on a flame retardant surface.
Thermal and Mechanical Injury
Certain components such as heat sinks, power regulators, and processors may be hot. Heatsink fans are not guarded. Power supply fan may be accessible through guard. Care should be taken to avoid contact with these components.
Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan.
Electro-Magnetic Interference (EMI)
This equipment has not been tested for compliance with emission limits of FCC and similar international regulations. Use of this equipment in a residential location is prohibited. This equipment generates, uses and can radiate radio frequency energy which may result in harmful interference to radio communications. If this equipment does cause harmful interfence to radio or television reception, which can be determined by turning the equipment on and off, the user is required to take measures to eliminate this interference.
Telecommunications Port Restrictions
The wireline telecommunications ports (modem, xDSL, T1/E1) on this product must not be connected to the Public Switched Telecommunication Network (PSTN) as it might result in disruption of the network. No formal telecommunication certification to FCC, R&TTE Directive, or other national requirements have been obatined.
Electrostatic Discharge (ESD) Warning
A properly grounded ESD wrist strap must be worn during operation/installation of the boards, connection of cables, or during installation or removal of daughter cards. Failure to use wrist straps can damage components within the system.
CE EMI Conformity Caution
This development board is delivered conforming to relevant standards mandated by Directive 2014/30/EU. Because of the nature of programmable logic devices, it is possible for the user to modify the development kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as a result of modifications to the delivered material is the responsibility of the user of this development kit.
In Default Switch and Jumper Settings, updated value for S3.1 in DIP Switch Settings table to OPEN/OFF/1
In Switches, in DIP Switch Settings table, updated default value of S3.1 to 1. Changed values in S3 description to 01 - Internal Oscillator. Set to 01 by default.