This user guide provides a brief overview of the various tabs in the device-specific PDN tool 2.0. It provides conceptual information and is common for all devices. You can quickly and accurately design a robust power delivery network with the PDN tool 2.0. This is done by calculating an optimum number of capacitors that meet the target impedance requirements for a given power supply.
|Operating System||Excel Versions|
|Windows 10 Professional (64-bit)||Office 2010 and 2016|
|Windows 8.1 Professional (32-bit)||Office 2007, 2010, and 2013|
|Windows 8.1 Professional (64-bit)||Office 2010 and 2013|
|Windows 7 (64-bit)||Office 2010|
The Intel PDN tool 2.0 helps PCB designers estimate the number, value, and type of decoupling capacitors needed to develop an efficient PCB decoupling strategy. It allows you to do this during the early design phase, without going through extensive pre-layout simulations.
The PDN tool 2.0 is a Microsoft Excel-based spreadsheet that calculates an impedance profile based on your input. For a given power supply, the spreadsheet only requires basic design information to calculate the impedance profile and the optimum number of capacitors to meet the desired impedance target (ZTARGET). Basic design information includes the board stackup, transient current information, and ripple specifications, for example. The tool also provides the device- and power rail-specific PCB decoupling cut-off frequency (FEFFECTIVE). The results obtained through the PDN tool 2.0 are intended only as a preliminary estimate and not as a specification. For an accurate impedance profile, Intel recommends a post-layout simulation approach using any available EDA tool, such as Cadence PowerSI, Ansys SIWave, and Cadence Allegro PCB PI.
There are two versions of the PDN tool 2.0. One version is for 20-nm devices (which also includes the 14-nm Intel® Stratix® 10 devices), and one version is for all other devices listed below. The device families supported by the Intel device-specific PDN tool 2.0 are shown at the top of the Release Notes tab and they include:
- 14-nm devices:
- Intel® Stratix® 10 GX
- 20-nm devices:
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- 28-nm devices:
- Arria V
- Arria V GZ
- Cyclone® V
- Stratix® V
- 40-nm devices:
- Arria II GZ
- 55-nm devices:
- Intel® MAX® 10
- 60-nm devices:
- Cyclone® IV E and GX
The PDN tool 2.0 provides two parameters for guiding PCB decoupling design: ZTARGET and FEFFECTIVE.
The PDN tool 2.0 is based on a lumped equivalent model representation of the power delivery network topology.
For a first order analysis, the VRM can be simply modeled as a series-connected resistor and inductor as shown above. This is a result of the typical proportional, integral, derivative (PID) voltage regulation loop compensation configuration of many regulators. The VRM has a very low impedance and can respond to the instantaneous current requirements of the FPGA up to between 50 kHz and 150 kHz, depending on the voltage regulation loop crossover (0 dB) frequency.
The equivalent series resistance (ESR) and equivalent series inductance (ESL) values can be obtained from the VRM manufacturer. At higher frequencies, the VRM impedance is primarily inductive, making it incapable of meeting the transient current requirement.
PCB decoupling capacitors are used for reducing the PDN impedance up to 50-100 MHz. The on-board discrete decoupling capacitors provide the required low impedance. This depends on the capacitor-intrinsic parasitics (RcN, CcN, LcN) and the capacitor mounting inductance (LmntN). The inter-planar capacitance between the power-ground planes typically has lower inductance than the discrete decoupling capacitor network, making it more effective at higher frequencies up to 100 MHz. As frequency increases, the PCB decoupling capacitors become less effective. The limitation comes from the parasitic inductance seen with respect to the FPGA. FPGA parasitic inductance includes capacitor mounting inductance, PCB spreading inductance, ball grid array (BGA) via inductance, and packaging parasitic inductance. All of these parasitics are modeled in the PDN tool 2.0 to capture the effect of the PCB decoupling capacitors accurately. To simplify the circuit topology, all parasitics are represented with lumped inductors and resistors despite the distributed nature of PCB spreading inductance.
The change of dynamic component of PDN current gives rise to voltage fluctuation within the PDN, which may lead to logic and timing issues. You can reduce excessive voltage fluctuation by reducing PDN impedance. One design guideline is target impedance, ZTARGET. In the frequency domain, voltage fluctuation across a circuit at a frequency is proportional to the current flow through the circuit, and the impedance of the circuit at the frequency according to Ohm’s law. ZTARGET is defined using the maximum allowable noise tolerance and dynamic current change, and is calculated as follows.
For example, the dynamic current of a 1.8 V power rail is 2 A. The worst case dynamic current change is 50% of the dynamic current. The noise tolerance of the power rail is 5% of the nominal voltage. The desired PDN target impedance for decoupling design is calculated as follows:
To accurately calculate the ZTARGET for any power rail, you must know the following information:
- The maximum dynamic current change requirements for the FPGA that is powered by
the power rail under consideration. You can obtain this information from respective
device datasheet. You can calculate the maximum dynamic current change of a device
using the maximum dynamic current and the dynamic current change percentage.
Note: The dynamic current is intended to parameterize the high-frequency current draws required to provide the energy for CMOS transistors changing state. In the case of the core rail, the transients are generated by switching inside the FPGA core. Thus, a design which involves extensive logical switching generates higher % transients (dynamic current change) than a more static design. The dynamic current change magnitude could be higher if the dynamic current is higher. For information about default settings of the dynamic current change percentage for major FPGA rails, refer to the table in the Introduction tab of the PDN tool 2.0.Note: You can obtain accurate estimations on the maximum dynamic current for Intel® FPGA devices using the PowerPlay® Early Power Estimator (EPE) tool or the Intel® Quartus® Prime PowerPlay® Power Analyzer tools. When using the data from the EPE, be sure to use only the dynamic power for each section for the PDN calculation.
- The maximum allowable noise tolerance on the power rail is given as a percentage of the supply voltage.
Device switching activity leads to transient noise (high frequency spikes) seen on the power supply rails. This noise can cause functionality issues if they are too high. The noise must be damped within a range defined as a percentage of power supply voltage. The recommended values for the maximum allowable noise tolerance are listed in the respective device datasheet and in the Introduction tab of the PDN tool 2.0. Different rails have different specifications because of their sensitivity to the transient voltage noise as well as how much current is used by the power rail.
Refer to the Introduction tab of the PDN tool 2.0 for more information about ZTARGET.
|Rail Name||Default Voltage (V)||Noise Tolerance (%) 1||Dynamic Current Change (%) 1||Description|
|VCC||0.8 - 0.94 2||5||30 - 50||Core (30% for high dynamic current; 50% for low dynamic current)|
|VCCERAM||0.9||5||50||Programmable Power Tech Aux|
|VCCR_GXB||1.03/1.12 2||3||30||Transceiver RX Analog|
|VCCT_GXB||1.03/1.12 2||2||60||Transceiver TX Analog|
|VCCPT||1.8||5||50||Programmable Power Tech|
|VCCH_GXB||1.8||3||15||Transceiver I/O Buffer Block|
|VCCP||0.8 - 0.94 2||5||33||Periphery Power Supply|
|VCCBAT||1.2/1.5/1.8||5||100||Battery Back-up Power Supply|
As previously described, a capacitor reduces PDN impedance by providing a least-impedance route between power and ground for transient current. Impedance of a capacitor at high frequency is determined by its parasitics (ESL and ESR). For a PCB with capacitors mounted, the parasitics include not only the parasitic from the capacitors themselves but also those associated with mounting, PCB spreading, and packaging. Therefore, PCB capacitor parasitics are generally higher than on-die capacitor parasitics. As a result, decoupling using PCB capacitors becomes ineffective at higher frequencies. Using PCB capacitors for PDN decoupling beyond their effective frequency range brings no improvement to PDN performance and raises the bill of materials (BOM) cost.
To help reduce over-design of PCB decoupling, this release of the PDN tool provides a suggested PCB decoupling design cut-off frequency (FEFFECTIVE) as another guideline. You only need to design PCB decoupling that keeps ZEFF under ZTARGET up to FEFFECTIVE. ZEFF is the impedance profile of the PCB design and includes all PDN-related design parasitics, including:
- VRM R and L
- PCB spreading R and L
- Plane R and C
- Decoupling capacitors
- BGA_via R and L
FEFFECTIVE defines the effective frequency of on-board decoupling capacitors.
Refer to Troubleshooting ZEFF if the ZEFF is too high or the number of capacitors for decoupling becomes too high.
|Release_Notes||Provides the legal disclaimers, the revision history of the tool, and the user agreement.|
Displays the schematic representation of the circuit that is modeled as part of the PDN tool 2.0. It also provides the following related information:
|System_Decap||The principal tab that allows you to decouple your system. It displays by default when you launch the application. This tab provides an interface to enter your power sharing scheme for a selected FPGA device and derive the decoupling based on the input.|
|Stackup||Provides an interface to enter your stackup information into the PDN tool.|
|Library||Points to various libraries (capacitor, dielectric materials, and so on) that are called by other tabs. You can change the default values listed as part of these libraries.|
|BGA_Via||Provides an interface to calculate the BGA mounting inductance based on design-specific via parameters and the number of vias.|
|Plane_Cap||Provides an interface to calculate the plane capacitance based on design-specific parameters.|
|Cap_Mount||Provides an interface to input design-specific parameters for calculating the capacitor mounting inductance for two different capacitor orientations (Via on Side [VOS] and Via on End [VOE]).|
|X2Y_Mount||Provides an interface to input design-specific parameters for calculating the capacitor mounting inductance for X2Y type capacitors.|
|Enlarged_Graph||Provides an enlarged view of the Z-profile shown in the System_Decap tab.|
The System_Decap tab is divided into the following sections:
- Device selection
- Power rail data and configuration
- VRM Data
- Rail group summary
- VRM impedance
- BGA Via
- Decoupling selection
- Result summary
- Select the Family/Device using the
In the 20-nm Pro version of the PDN tool, choose Intel® Stratix® 10, Intel® Arria® 10, or Intel® Cyclone® 10 GX devices. In the 20 nm Standard version of the tool, choose Intel® MAX® 10 devices. In the 28 nm PDN tool, choose all other devices.
- Select your device and the package type from the Available Devices drop-down list.
- Select your desired power rail configuration from the Power Rail Configuration
The Power Rail Configuration list includes custom and pre-defined configurations. When you select a pre-defined configuration, the tool sets the suggested power rail grouping automatically.
The drop-down selections are based on examples from the pin connection guidelines for the device. Select the one that most closely matches your design, and use it as a basis for entering your design data. Refer to the pin connection guidelines for your device.
The tool updates the list of power rails and the contents in the power rail configuration sections based on your selections.
the power supply voltage in the Voltage
column for each power rail listed in Area 1 by selecting a value from the
pull-down menu, or by manually entering your own
Note: You must enter the total dynamic current consumption of related power rails before you can use the system decoupling function.
You can optionally adjust the recommended number up or down slightly based on knowledge of the intended application.
Enter the current consumption in the I dynamic column for each power rail.
The earliest data from the PowerPlay® Early Power Estimator (EPE) can provide good values for the current entries. The EPE delivers bulk data for the transceiver channels. Each bank of transceiver channels should be assigned the total EPE value divided by the number of banks. Later in the design cycle, the Intel® Quartus® Prime Power Play Power Analyzer (PPPA) can derive much better data for each bank rail.
Setup your device power sharing scheme in Area 2.
Figure 6. Power Rail Data and Power Sharing Scheme SectionThis configuration is an example of how this section of the spreadsheet should look. Every design will vary depending on the device chosen and the power rail configuration selected.
The current usage for each rail should be entered in the I dynamic column in Area 1. Note that, for the VCC rail, only the dynamic current usage should be entered from the Early Power Estimator.
Each column in Area 2 represents a power group in your system. Add or remove a power group using the Add Group or Remove Group buttons. The first row of each group is the Regulator/Separator type. Set the source type for the power group and available options from the pull-down list as switcher, linear, or filter.
The second row is the Parent Group type. The available options for this row are None and the number representing all listed power groups. Input your power sharing hierarchy in this column, and set the power rail connection using the remaining rows.Note: The PDN tool 2.0 defines the power rail configuration using the Parent/Child power group. A power group is a child power group if it attaches to another power group at its input. The other power group is the parent group in this case. A parent group can have multiple child groups. A parent power group number is required for the child group. The parent group number of a parent power group is assigned to None because the group has no parent group.
The available Area 2 rail options are:
Note: Two I/O rails are related if their output activities are synchronous. For example, when two VCCIO rails are assigned to the same memory interface. The maximum current will usually be reached at the same time for these related rails. As a result, the total current of related rails equals the sum of the current of all shared rails. The total current of unrelated rails is calculated using the root-sum-square (RSS) method.The PDN tool 2.0 sets the default power rail sharing configuration based on the selected Intel-recommended power rail configuration listed above. Make changes to better match your design.Note:
- blank — Device rail does not connect to the power group.
- x — Device rail connects to the power group.
- x/related— Device rail connects to the group, and its activity is related to other rails that connect to the same group. You must select x/related if that VCCIO/VCCPT power rail is related to other rails within the same power rail group.
In the rail connection matrix, you can change the voltage of a rail without disconnecting it from a regulator group. However, all other rails connected to the same group must be able to change to the new voltage.Figure 7. Changing Voltage for All Rails in a Group
In this section, you can find a list of the following calculated key parameters of all power groups:
- Total Current
- Dynamic Current Change
- Noise Tolerance
- Core Clock Frequency
- Current Ramp Up Period
These options allow you to customize how the data is collected or analyzed.
The Dynamic Current Change parameter has a pull-down menu with the following options:
Dynamic current change percentage requires a lot of diligence. The EPE and PPPA both deliver values for current usage that include:
- the maximum static current (does not vary)
- the maximum current usage by the active elements
This calculation yields both a very high total current and a fairly high dynamic current usage. Calculations for a value to insert into the Dynamic Current Change field could yield a value much lower than the auto-populated value, which represents a safe engineering value.
The Noise Tolerance parameter has a pull-down menu with the following options:
Some PDN tool variants allow you to add data for the Core Clock Frequency and Current Ramp Up Period parameters using the pull-down menus. These values tell the tool how to calculate the current ramp up period for transient events, sometimes reducing transient current changes. The values relate to how fast the clock for the section is running, and the length of the data pipeline. Given a transient change in the input data, there are clock cycles in the pipeline for the algorithm to deliver the results. If the input data change activates a broad yet short pipeline, the transient is abrupt. This results in a large current change for the number of logic elements being used. If the pipeline is narrow and long, the overall change in current usage is proportionately smaller.
You can set the Core Clock Frequency parameter to a High, Medium, Low, or Custom set of input frequencies. The Custom option allows you to enter a specific input frequency.
The Current Ramp Up Period parameter allows you to specify the number of clock cycles consumed by the pipeline. You can select a Long, Medium, Short, or Custom setting.
Core Clock Frequency and Current Ramp Up Period options are highly dependent upon the core utilization setup in Intel® Quartus® Prime. Thus, options in the PDN tool can be used as a reference.
Enter the VRM impedance values for the regulators. Use the pull-down menu to enter data for VRM Resistance and VRM Inductance.
There are three ways to change the voltage regulator module (VRM) parameters. Depending on what you select in the VRM Impedance pull-down menu, you can:
- Select Custom and set your desired Rvrm and Lvrm values.
- Select Library and get the suggested typical Rvrm and Lvrm values. This depends on the type of regulator (for example, switching, linear, or filter) you have selected.
- Select Ignore and Rvrm and Lvrm will not be considered as design parameters.
- For switching regulators, you can choose a specific Enpirion® VRM (based on ordering code) directly in the pull-down menu.
The PDN tool can help you select the appropriate Enpirion VRM module to use for each power supply in your system.
The BGA Via table shows the L and R values per via. You can set the tool to Calculate, Custom, Default, or Ignore. For a fully customized workflow in which each rail group can have different settings, set the total effective R and L values in the BGA Via section to match your system.
If you set the BGA Via table to Calculate or Ignore, the System_Decap tab uses the same global settings for all rail groups.
- Select the Plane_Cap tab in the PDN tool 2.0.
- Set the parameters to match your system, and notice that the Total planar capacitance and Total sheet resistance values are updated automatically.
- In the System_Decap tab, select the Custom option for each group where a custom plane is required.
- Enter the calculated Ctotal and Rtotal values into the Plane section of the System_Decap tab.
Setting the Plane table to Calculate or Ignore causes the System_Decap tab to use the same global settings for all rail groups.
- Select the Library tab in the PDN tool 2.0.
- Set the parameters in the Spreading R and L table to match your system.
- Examine the range of spreading R and L values to determine if you need a custom R and L. If a custom R and L is warranted, select Custom in the System_Decap tab and set the R and L values directly.
Setting the Spreading table to Low, Medium, High, or Ignore causes the System_Decap tab to use the same global settings for all rail groups.
Each group of power rails shares the same regulator. Therefore, separate power rail groups have separate regulators. However, they might share the same power plane layer (but separate power islands with different dimensions). Alternatively, each power rail group can be located on a different power plane layer.
- If the regulator groups share the same power plane, select the same Layer
Number under BGA Via in the
Figure 9. Set the Layer Number
- Perform these steps in the Stackup tab:
- Complete the Stackup Data table.
- Click Import Geometries.
Figure 10. Complete the Stackup Data Table
- Perform these steps in the Plane_Cap tab:
- Specify the dimensions of the area allocated to each regulator group.
- Change the import target from All to the group ID.
- Click Import Plane R&C.
Figure 11. Import the Plane R&C
You can set Feffective to Calculate or Override. Select the Calculate option to use the Intel-recommended cut off frequency based on package and die parasitics.
You can set Decoupling to Manual or Auto. If you select the Auto option, any change you make to the system is automatically reflected in the decoupling solution. You can also view the impedance chart per rail group or VRM.
Selecting the Manual option allows you to:
- Lock in calculated decoupling solutions from being further optimized by any changes made to the System_Decap tab.
- Add or remove the number and type of decoupling capacitors in the Results Summary section. You can see its immediate impact on the impedance profile curve.
You can find the list of the number and type of capacitors used for each group, and the summary of all the capacitors used. The values in each column indicate the number of capacitors needed of each value for each rail.
The results section may show a very large number of capacitors required to decouple some power rails. Changes in various worksheets that supply data to this worksheet will have a substantial effect on the capacitors required.
- Select the appropriate device family or device.
- Set up the stack up information in the Stackup tab.
The tool updates the power rail connection configuration to the scheme recommended in the Pin Connection Guidelines.
Ensure that the
following default parameters match your system, and make the necessary changes
- power rail configuration
- relativity of power rails within the same power group
- power group layer
- number of power/ground Via pairs
- DC voltage supply for VRM module
- decoupling cap location
- Enter the projected current consumption of each power rail.
Enter the PCB stackup information of your design in the Stackup tab. This tab updates related data in the BGA_Via, Plane_Cap, Cap_Mount and the X2Y_Mount tabs. The stackup information in this tab is also used for the System_Decap tab. Follow the instructions provided at the beginning of the tab to fill in the content for this tab.
The Stackup Data section is where you enter board dimension data and other parameters, such as board stackup settings, power via, and dielectric material.
This section lists the complete stackup of your board. You can modify content in the section to better match your board design. The last column in the section is the PWR plane types. In a single rail analysis case, assign the layer where the power rail is located as target, and the ground layer that the power rail refers to as reference.
|Construct Stackup||Populates the Full Stackup section to the number of layers defined in the Stackup Data section.|
|Import Geometries||Updates geometry parameters in the BGA_Via, Plane_Cap, Cap_Mount, and X2Y_Mount tabs using your input from the Stackup Data section. The tool also checks that the PWR Planes column in the Full Stackup section has only one target layer, and provides a warning for this error.|
|Proceed to System Decap||Opens the System_Decap tab.|
The BGA Via tab calculates the vertical via loop inductance under the BGA pin field.
Enter the layout-specific information such as via drill diameters, via length, via pitch, and the number of power/ground via pairs under the BGA in the BGA Via Inductance table. The tool calculates the effective via loop inductance and resistance value. You can save the change made to the tab, restore the changes, or restore the tab back to the default settings.
The Plane Cap tab calculates the distributed plane capacitance in microfarads (µF) that is developed between the power/ground planes based on the parallel plate capacitor equation.
Enter the design specific information such as plane dimensions, plane configuration and the dielectric material used in the Planar Capacitance table. The tool calculates a plane capacitance value. You can save custom values, restore custom values, or restore the default settings.
The Import Plane R&C button inserts the data for the planar capacitance into the regulator group data.
The Cap Mount tab calculates the capacitor mounting inductance seen by the decoupling capacitor.
The capacitor mounting calculation is based on the assumption that the decoupling capacitor is a two-terminal device. The capacitor mounting calculation is applicable to any two-terminal capacitor with the following footprints: 0201, 0402, 0603, 0805, and 1206. Enter all the information relevant to your layout, and the tool provides a mounting inductance for a capacitor mounted on either the top or bottom layer of the board. Depending on the layout, you can choose between VOE (Via on End) or VOS (Via on Side) to achieve an accurate capacitor mounting inductance value. Generally, VOS can have lower mounting inductance due to a smaller via pitch. Also, X2Y cap can be considered as a solution for a space-limited design.
If you plan to use a footprint capacitor other than a regular two-terminal capacitor or X2Y capacitor for decoupling, you can skip the Cap Mount tab. In this case, you can directly enter the capacitor parasitics and capacitor mounting inductance in the Library tab (under the Custom field in the Decoupling Cap section of the library). As with the other tabs, you can save the changes made to the tab, restore the changes, or restore the tab back to the default settings.
You must pay special attention to the via lengths for the capacitors. Via inductance comprises a substantial portion of the PDN impedance.
The X2Y Mount tab calculates the capacitor mounting inductance seen by the X2Y decoupling capacitor.
Enter all the information relevant to your layout in the X2Y CAP Mounting Inductance table. The tool then provides a mounting inductance for an X2Y capacitor mounted on either the top or bottom layer of the board. You can save the changes made to the tab, restore the changes, or restore the tab back to the default settings.
The Library tab stores all the device parameters that are referred to in the other tabs.
You can change each of the default values listed in the respective sections to meet the specific needs of your design.
The decoupling capacitors section also provides the option for the user defined capacitors (such as User1 through User4). You can define the ESR and ESL parasitics for the various footprints and enter the corresponding capacitor value in the System_Decap tab. Choose the corresponding footprint when defining the capacitor values.
The bulk capacitors section contains the commonly used capacitor values for decoupling the power supply at mid and low frequencies. You can change the default values to reflect the parameters specific to the design.
The X2Y decoupling capacitors section contains the default ESR and ESL values for the various X2Y capacitors in the 0603, 0805, 1206, and 1210 footprints. You also can replace the default ESR and ESL values with your own commonly used custom values.
This section allows you to directly enter the values for effective via loop inductance under the BGA and plane capacitance during the pre-layout phase when no design-specific information is available.
If you have access to design-specific information, you can ignore this section and enter the design-specific information in the Plane Cap and BGA Via tabs that calculate the plane capacitance and the BGA via parasitics, respectively.
The VRM section lists the default values for both the linear and switcher regulators. In the Custom field, you can change the VRM parasitics listed under the linear/switcher rows or add the custom parasitics for the VRM relevant to the design.
This library provides various options for the default effective spreading inductance values that the decoupling capacitors see with respect to the FPGA. These values are based on the quality of the PDN design. You can choose a Low value of effective spreading inductance if you have optimally designed your PDN Network. Optimum PDN design involves implementing the following design rules:
- PCB stackup that provides a wide solid power/ground sandwich for a given supply with a thin dielectric between the planes. The thickness of the dielectric material between the power/ground pair directly influences the amount of spreading/loop inductance that a decoupling cap can see with respect to the FPGA.
- Placing the capacitors closer to the FPGA from an electrical standpoint.
- Minimizing via perforations in the power/ground sandwich in the current path from the decoupling caps to the FPGA device.
Due to layout and design constraints, the PDN design may not be optimal. In this case, you can choose either a Medium or High value of spreading R and L. You can also change the default values or use the Custom field listed in the library specific to the design.
This library lists the dielectric constant values for the various commonly used dielectric materials. These values are used in the plane capacitance calculations listed under the Plane_Cap tab. You can change the values listed in this section.
If you change the default values listed in the various sections in the Library tab, you can save the changes by clicking Save Custom. You can restore the default library by clicking Restore Default located at the top right-hand corner of the Library page. You can also restore the saved custom library by clicking Restore Custom.
You must decouple to an FEFFECTIVE higher than what is calculated for the power rails of some device families. In this case, you must set the FEFFECTIVE option to Override in the System_Decap tab. The PDN tool 2.0 then uses the FEFFECTIVE value entered here.
In the Enlarged_Graph tab, you can view the enlarged Z-profile plot. The PDN tool 2.0 switches to this tab when you click on the Z-profile plot in the System_Decap tab. You can go back to the System_Decap tab when you click the Return button.
PCB decoupling keeps the PDN ZEFF smaller than ZTARGET with the properly chosen PCB capacitor combination up to the frequency where the capacitance on the package and die take over the PDN decoupling. This procedure uses the PDN tool 2.0 in different power rail configurations and provides design examples using the Intel® Stratix® 10 device PDN tool.
The PDN tool 2.0 provides an accurate estimate of the number and types of capacitors needed to design a robust power delivery network, regardless of where you are in the design phase. However, the accuracy of the results depends highly on the user inputs for the various parameters.
If you have finalized the board stackup and have access to board database and layout information, you can proceed through the tabs and enter the required information to arrive at an accurate decoupling scheme.
In the pre-layout phase of the design cycle when you do not have specific information about the board stack-up and board layout, you can follow these instructions to explore the solution space when finalizing key design parameters such as stackup, plane size, capacitor count, capacitor orientation, and so on.
In the pre-layout phase, ignore the Plane Cap and Cap Mount tabs and go directly to the Library tab when you do not have the layout information. If available, enter the values shown below in the Library tab. To use the default values, go directly to the System_Decap tab to begin the analysis.
- Enter the ESR, ESL, and Lmnt values for the capacitors listed in the Custom field.
- Enter the effective BGA via parasitics for the power supply being decoupled in the BGA Via & Plane Cap field.
- Enter the plane capacitance seen by the power/ground plane pair on the board for the power supply in the BGA Via & Plane Cap field.
- Enter the VRM parasitics, if available, in the Custom row of the VRM field.
- Enter the effective spreading inductance seen by the decoupling capacitors in the Custom row of the Spreading R and L field.
A power supply connects to only one power rail on the FPGA device in a single-rail scenario. The PDN noise is created by the dynamic current change of the single rail. You determine ZTARGET and FEFFECTIVE based on the parameters related to the selected rail only.
The PDN tool 2.0 provides two ways to derive a decoupling network. You can set up the tool with the information needed and let the tool derive the PDN decoupling for your system. You can also manually enter the information and derive decoupling. To derive the desired capacitor combination:
- Select the device/power rail to work with.
- Select the parameter settings for the PDN components.
Enter the electric
parameters to set ZTARGET and FEFFECTIVE.
You need to have a good estimate of the parameters entered to derive the proper decoupling guidelines (ZTARGET and FEFFECTIVE). Although you need to determine those guidelines based on the worst-case scenario, pessimistic settings result in hard-to-achieve guidelines and over design of your PCB decoupling.
Derive the PCB
You must adjust the number and value of the PCB capacitors in the Decoupling Capacitor (Mid/High Frequency) and Decoupling Capacitor (Bulk) fields to keep the plotted ZEFF below ZTARGET until FEFFECTIVE. You can derive the decoupling for the selected power rail manually. You can also select the Auto Decouple button and let the PDN tool 2.0 automatically determine a decoupling solution. If you are not able to find a capacitor combination that meets your design goal, you can try to change the parameters at 2. For example, you can reduce the BGA via inductance used in the Calculate option by reducing the BGA via length in the BGA_VIA tab and using the low option for plane spreading. These changes reduce parasitic inductance and make it easier to achieve your decoupling goal. To achieve the low spreading setting, you must place the mid to high frequency PCB capacitors close to the FPGA device. You also must minimize the dielectric thickness between the power and ground plane. Refer to Troubleshooting ZEFF if the ZEFF is too high or the number of capacitors for decoupling becomes too high.
If you are not able to meet the ZTARGET requirement with the changes above, the PDN in your design may have reached its physical limitation under the electrical parameters you entered for ZTARGET and FEFFECTIVE. You should re-examine these parameters to check if they are overly pessimistic.
The PDN tool 2.0 calculated that ZTARGET is 0.0027 Ω and FEFFECTIVE is 13.58 MHz. The figure above shows one of the capacitor combinations that you can select to meet the design goal. As shown in the plot, ZEFF remains under ZTARGET up to FEFFECTIVE. There are many combinations, but the ideal solution is to minimize the quantity and the type of capacitors needed to achieve a flat impedance profile below the ZTARGET.
It is a common practice that several power rails in the FPGA device share the same power supply. For example, you can connect VCCPT, VCCA_PLL, and VCCA_FPLL rails that require the same supply voltage to the same PCB power plane. This can be required by the design, such as in the memory interface case. This can also come from the need to reduce bill of materials (BOM) cost. You can use the System_Decap tab to facilitate the decoupling design for the power sharing scenarios.
When deriving decoupling capacitors for multiple FPGAs sharing the same power plane, each FPGA should be analyzed separately using the PDN tool 2.0. For each FPGA design, combine the required power rails as described above and analyze the decoupling scheme as if the FPGA was the only device on the power rail, taking note of how the current is divided across the devices.
High frequency decoupling capacitors are meant to provide the current needed for AC transitions, and must be placed in a close proximity to the FPGA power pins. Thus, the PDN tool 2.0 should be used to derive the required decoupling capacitors for the unique power requirements for each FPGA on the board.
The power regulators must be able to supply the total combined current requirements for each load on the supply, but the decoupling capacitor selections should be analyzed on a single FPGA basis.
When the decoupling mode is set to Auto, this may result in a ZEFF value that is too high. This can happen when the PCB parameters you entered result in an inefficient PDN, and the current to be decoupled by the PCB are unrealistically high.
With difficult PCB and current parameters, auto decoupling continues to add decoupling capacitors until it determines they have little effect. This results in hundreds of capacitors. You can achieve decoupling schemes with similar performance manually using far fewer capacitors.
As well as decoupling manually, you can reduce the decoupling burden by accurately estimating your current requirements and making your PCB more efficient. You may be able to achieve reduced PCB current requirements in the following ways:
- Estimating realistic current requirements in the PowerPlay® Early Power Estimator (EPE).
- Entering realistic toggle rate figures for the logic in the EPE. Unrealistically high toggle rates dramatically increases dynamic current requirements.
- Entering realistic logic requirements in the EPE.
- Entering realistic clock frequencies in the EPE.
- Using the Intel® Quartus® Prime software ( PowerPlay® Power Analyzer) PPPA and .vcd simulation entry for accurate current requirement estimation.
- Considering Root Sum Squared (RSS) averaging for shared power supply rails. Refer to the Introduction tab of the PDN tool for more information on this method.
You can make the PCB more efficient in the following ways:
- Increasing inter-plane capacitance of your Power (PWR) and Ground (GND) plane pair by reducing their dielectric thickness.
- Increasing inter-plane capacitance of your PWR and GND plane pair by increasing their surface area.
- Reducing loop inductance from the PWR and GND plane pair to the FPGA. You can do this by moving them closer to the surface of the PCB where the FPGA is mounted.
- Reducing loop inductance from the high frequency decoupling capacitors to the PWR and GND plane pair. You can do this by placing them on the surface of the PCB that is closest to the planes.
- Using Via On Side (VOS) instead of Via On End (VOE) capacitor mounting topologies to help at high frequencies.
- Using ultra-low Effective Series Inductance (ESL) mounting capacitors to help at high frequencies, for example, X2Y package style.
- Using ultra-low Effective Series Resistance (ESR) bulk capacitors to help at low frequencies.
- Considering larger vias with less ESL.
Realistic tool entry can make decoupling easier to achieve. The following factors affect the calculation of ZTARGET:
- An increase in dynamic current reduces ZTARGET and makes decoupling difficult to achieve. See the guidelines above.
- Enter realistic noise or ripple figures into the PDN tool. Use the noise figure listed in the device and rail specific table in the Introduction tab of the PDN Tool. Unrealistic ripple requirements reduce ZTARGET and make decoupling difficult.
- Enter realistic transient % figures into the PDN tool. Use the transient % figure listed in the device and rail specific table in the Introduction tab of the PDN Tool. Unrealistic transient % requirements reduce ZTARGET and make decoupling difficult.
The PDN Tool 2.0 includes the following new pessimism removal features to make decoupling the large core current manageable:
- Core clock frequency
- Current ramp up period
- Click the System_Decap tab.
- Select your Device and click Yes in the confirmation dialog box.
- Click the Stackup tab.
Input your stackup values for the following parameters:
- Number of Layers
- Drill Size
- BGA Via pitch
- Foil Thickness
Select a dielectric material from the Dielectric
Material drop-down menu.
Note: If you are using a custom dielectric material, skip this step and proceed to the Using a Custom Dielectric Material section.
Click Construct Stackup, then click
Yes in the Construct Stackup
confirmation dialog box.
The Full Stackup section updates based on your inputs.
Enter the Thickness values for each layer in the
Full Stackup table, then click Import
Figure 22. Full Stackup Table
- Save your data to prevent data loss.
Click the Library tab, then enter the
Er value for Custom 1 or
Custom 2 as necessary.
Figure 23. Er Value for Custom Dielectric Material
- Click the Stackup tab, then select either Custom 1 or Custom 2 from the drop-down menu.
- Click Construct Stackup, then click Yes in the confirmation dialog box.
- Click the System_Decap tab.
- Select a regulator type from the Regulator/Separator drop-down menu for Group #1.
Select either x or x/related for
each selected power rail.
Note: One power group can have one or more power rails depending on your power configuration. Refer to the Introduction tab in the PDN tool for a complete description of the tool options.
- Obtain the dynamic current estimations from the Report tab of the PowerPlay® Early Power Estimator (EPE) tool.
Enter these values in the Imax column of the
System_Decap tab in the PDN tool.
Note: You can always add your own additional engineering margin on top of the EPE estimation based on your system design experience and the Power Model Accuracy in the EPE tool.
With these options enabled, the ZTARGET curve relaxes from certain frequencies based on the inputs.
If a VRM model is available from the vendor, you can select the Custom option to replace the default values by directly overriding the new values.
The tool automatically calculates the parasitics when you enter your expected layer number in the Layer Number field by overriding for power rail location in the stackup.
- Click the Stackup tab.
Enter your expected plane length and width values in the Plane
Length and Plane Width fields,
This is the best method for estimating if the layout design is already in progress (see the following figure).Figure 28. Plane Size EstimationThe tool only measures the plane size from the VRM to the FPGA.
- Select which layers you want to use as target (power) and reference (ground, two layers maximum) in the Full Stackup table.
- Click Import Geometries on the left side of the Full Stackup table.
Click the Plane_Cap tab.
The tool automatically updates the plane parasitics.
Change the regulator group number in the Import the calculated Plane
R & Plane C to regulator Group field, then click
Import Plane R&C.
Figure 29. Plane_Cap Table
Click the System_Decap tab and verify that the tool has updated the
Note: The PDN tool does not support the multi-layered design for a single power. However, you can repeat 1 through 6 for each power layer, keeping the estimated parasitic numbers of each and combining capacitances of each power for final capacitance and calculating resistances of each power in parallel to get the final resistance. For example, if both layers nine and 10 of roughly the same size plane have one power rail, the tool calculates the parasitics based on one power and one reference layer in the Full Stackup table as shown in the figure below. Then, the final capacitance can be 0.0016 x 2 = 0.0032 µF and the final resistance can be 0.001 / 2 = 0.0005 Ω.Figure 30. Plane Parasitics
The default spreading setting is Low. Depending on the location of your decaps, you may also select Medium or High.
The following figure shows final decoupling recommendations based on the inputs in the tool. However, even though ZPDN meets the ZTARGET up to FEFFECTIVE, the number of capacitors, 301, are not suitable for the real design. Refer to the Optimization Method section for details about optimizing your results.
- Click the Library tab.
If there are RLC models with lower parasitics, replace the
existing capacitors with them.
Figure 33. Library of Capacitors
Replace bulky Tantal Polymer capacitors with
Multi-layered Ceramic Capacitor (MLCC) caps with similar
electrical/thermal characteristics. 100uF, 220uF, and 330uF caps with
much lower ESR and ESL are available.
Using the decap library effectively in the PDN tool will result in a more accurate estimation.
- Use User and Custom options for additional capacitors.
- Replace bulky Tantal Polymer capacitors with Multi-layered Ceramic Capacitor (MLCC) caps with similar electrical/thermal characteristics. 100uF, 220uF, and 330uF caps with much lower ESR and ESL are available.
Change the Decoupling mode from
Auto to Manual.
Figure 34. Manual Decoupling Results Summary - Pre-Optimization
Observing the impedance plot carefully, optimize the number of each
Figure 35. Manual Decoupling Results Summary - Post-Optimization, Round 1After optimizing manually, 301ea decaps are dramatically reduced to 124ea while maintaining a similar ZPDN profile (the red curve) under the same ZTARGET.Figure 36. Manual Decoupling Results Summary - Post-Optimization Results, Round 1A small amount of violation at different frequencies can reduce the number of decaps. Before and after results are shown below.
- Change Feffective option from Calculate to Override.
- Check whether or not the number remains the same.
If the number changes, write the recommended FEFFECTIVE, 10.18 MHz in the example below, into the
Figure 38. FEFFECTIVE Override
Change the Spreading
option from Low to Ignore.
Once the spreading option is ignored, the entire ZPDN will be a little lowered, which means more margin.Figure 39. Ignoring Spreading
Repeat the manual optimization for each cap as shown in Optimizing the Decap Count.
After the optimization process, only 48ea of 0402in capacitors (circled with a red box below) are estimated while the total allowable number of 0402in capacitors is 70ea. Also, the rest of the larger capacitors (circled with a blue box below) in this example can be populated in the BGA area. Final results are shown below. The total number of capacitors was decreased down to 77ea from the max limit of 301ea, including bulk capacitors, through round 1 and 2 of the optimization process.Note: The PDN tool result already includes the bulk capacitor solution for VRM. However, Intel recommends checking with the VRM vendor about the required output capacitance to check if the PDN tool estimation can cover the requirement. Enpirion models in the VRM library already include the required output capacitance. For the required capacitor combination, please refer to the datasheet of each VRM model.Figure 40. Manual Decoupling Results Summary - Post-Optimization, Round 2
The following results show the correlation between the PDN tool and the post-layout system PDN impedance profile (lower right figure) for one of Intel's development kit boards. In the post-layout analysis, the simple VRM model from the PDN tool was used. Since the PDN tool is already considering PKG and die parasitics, both results are well correlated.
|June 2017||2017.06.05||Made the following changes:
|December 2016||2016.12.09||Made the following changes:
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|September 2014||2014.09.12||Initial release.|