This application note describes a design example which demonstrates data alignment calibration using multiple Altera PHYLite for Parallel Interfaces IP cores.
- Data word alignment using Altera PHYLite for Parallel Interfaces dynamic configuration feature
- Using Nios II processor as configuration controller
- Provides I/O timing constraint guidelines between two Altera PHYLite for Parallel Interfaces instances
- Supports hardware testing
- Intel® Arria® 10 FPGA Development Kit (Device OPN: 10AX115S3F45E2SGE3)
- Loopback FPGA mezzanine (FMC) daughter card
- Intel® FPGA USB Download Cable
- Intel® Quartus Prime Design Suite® version 16.0
- Arria10_Phylite_Word_Alignment_Calibration.qar file.
- Follow the guidelines in Getting Started with the Design Store to download and install the reference design files.
- Open the reference design .qpf file after successfully installing the design templates.
Quartus® Prime software, open dut_INPUT.qsys and dut_OUTPUT.qsys files. Make sure the Altera PHYLite IP core has
the same configurations shown below:
Figure 1. General Tab Configuration for dut_INPUT ModuleFigure 2. Group 0 Tab Configuration for dut_INPUT ModuleFigure 3. General Tab Configuration for dut_OUTPUT ModuleFigure 4. Group 0 Tab Configuration for dut_OUTPUT Module
- In Quartus® Prime software, click on Assignments > Settings > TimeQuest Timing Analyzer.
In the Tcl Script File name, type in
phylite_interface_constraints.tcl and select
Run default timing analysis before running customer
Figure 5. Adding Interface Constraints Calculation Script
- Click Apply and OK.
- In the Quartus® Prime, click Processing > Start Compilation to compile the reference design.
The following steps are to setup the Arria® 10 FPGA development kit before running the reference design.
Arria® 10 FPGA development board switches to according
to the following figure.
Figure 6. Arria® 10 FPGA Development Board Switch Settings
Connect the loopback FPGA mezzanine (FMC) daughter card on the FMC loopback
Figure 7. Connection for Loopback FPGA Mezzanine (FMC) Daughter Card
- Connect the USB Download Cable to the Arria® 10 FPGA development kit and your host machine.
- Click Tools -> Programmer to program the <project directory> /master_image/top.sof file into the Arria 10 FPGA development board.
Follow the steps below to generate an executable and linking format (.elf) programming file. These steps are necessary if you would like to modify the phylite_dynamic_reconfiguration.c, phylite_dynamic_reconfiguration.h and hello_world.c files.
Quartus® Prime software
version 16.0 select Tools > Nios II Software Build Tools for
Figure 8. Nios II Software Build Tools for Eclipse
Create a new workspace when the Select a workspace window prompt appears.
Figure 9. Create New Workspace
Select File > New > Nios II Application and BSP from
Template in the Nios II - Eclipse window.
Figure 10. Nios II Application and BSP from Template
In the SOPC Information File
name parameter, browse to the location of phylite_nios.sopcinfo file in your host machine.
Click OK to select the file and Eclipse automatically
loads all CPU settings.
The phylite_nios.sopcinfo is created when generating phylite_nios.qsys.
- In the Project name parameter, specify your desired project name.
- Choose Hello World as the project template.
Click Finish to generate the project.
Quartus® Prime software creates a new directory named
software in the specified project
Figure 11. Nios II Application and BSP from Template Settings
Replace the following files from <project directory>/software reference design with the
files located in your new software directory.
- In the Nios II - Eclipse window, press F5 to refresh the window and reload the new files into the project.
- Click Project > Build Project.
- Make sure the <project_name>.elf file is generated in the new <project directory>/software/<project_name>/ directory.
These steps are guidelines to run the dynamic calibration and begin the data transfer for the reference design.Remove all other connected device in the programming device list during JTAG connection setup in Linux operating system.
Open two Nios II Command Shell prompts on your host machine:
Command prompt A is to display the dynamic calibration result. Command prompt B is used to run Nios II commands.
- In Windows operating system, go to Start > Programs > Altera > Nios II EDS and click on Nios II Command Shell (command prompt A).
- In Linux operating system, go to <Quartus software installation directory>\linux64\nios2ed directory and run nios2_command_shell.sh to launch command prompt A.
- Repeat the above step to launch second command prompt (command prompt B).
In the command prompt A , use the following command to run the
Nios II terminal application for result printouts.
In command prompt B, go to the project top directory.
cd <project directory>
Run the issp.tcl script once to reset
the system and clean up the instruction memory in the Nios II soft
quartus_stp -t issp.tcl top.qpf 1 0
In command prompt B, download the executable (<project_name>.elf) file into the FPGA and
start the dynamic calibration process with the following command:
nios2-download -r -g software/<project_name>/<projct_name>.elfYou may observe the passing dynamic calibration result displayed in command prompt A.
When the Nios II instruction memory is cleaned and calibration
is done, run the following command in command prompt B to reset the system,
start the random data transfer and capture internal signals.
quartus_stp -t issp.tcl top.qpf 1 1 1Note: You will see sent and received data displayed in command prompt B after running the command.
- Dynamic calibration result
- Random data transfer result
- The number of words being transferred
- The sent data value
- The expected data value
- The received data value
- The passing/failing status of the test
- Sent and received data.
- Indication of dynamic calibration has passed.
- Indication that the configuration is done.
- dut_INPUT module
- dut_OUTPUT module
- PLL module
- Avalon controller
- ATSO_DYN_CFG_CTRL module with Nios II processor
- Traffic generator
This module takes the input from Si570 Programmable Oscillator and provides reference clock to the Avalon controller and Altera PHYLite for Parallel Interfaces IP cores.
This Altera PHYLite for Parallel Interfaces IP core transfers data from ATSO_DYN_CFG_CTRL or traffic generator module to dut_INPUT module. During configuration and calibration mode, this module takes data from ATSO_DYN_CFG_CTRL module and send to dut_INPUT module. In normal operating mode, this module takes data from traffic generator and sends to dut_INPUT module.
This Altera PHYLite for Parallel Interfaces IP core receives data from dut_OUTPUT module. This module sends the received data to ATSO_DYN_CFG_CTRL module during configuration and calibration mode, and to traffic generator during normal operating mode for data verification.
The Avalon controller is responsible to perform address translation to retrieve the physical address of the strobe and data pins and sends reconfiguration commands to dut_OUTPUT module.
ATSO_DYN_CFG_CTRL with Nios II Processor Module
|Parallel I/O Module||Address Map||Description|
|phy_write_data||0x20||Sends calibration test data to dut_OUTPUT module.|
|phy_write_ctrl||0x30||Asserts rdata_en signal during calibration mode.|
|phy_read_data||0x40||Receives data from dut_INPUT module for comparison against test data.|
|phy_read_status||0x50||Receives rdata_valid signal from dut_INPUT module.|
|cal_mode||0x60||Asserts cfg_done signal to exit calibration mode and activates traffic generator module for data transfer for normal operating mode.|
Traffic Generator Module
Traffic Generator module is responsible for transmitting data to dut_OUTPUT and receiving data from dut_INPUT during normal operating mode. The module uses Linear Feedback Shift Register (LFSR) to generate random data for transmission. Traffic generator performs data comparison to the received data to ensure the strobe enable delay setting is configured correctly.
The data word alignment algorithm starts by Nios II processor setting the strobe enable delay and read valid enable delay of the dut_INPUT to the minimum read latency based on the FPGA core clock rate and the VCO frequency multiplier factor.
Next, Nios II processor asserts oe_from_core signal to initiate data transmission to dut_OUTPUT and sends a set of test data to the dut_OUTPUT.
The dut_OUTPUT transmit the test data to the dut_INPUT. The rcfg_data_from_core signals show the data value transmitted from dut_OUTPUT.
It is crucial to set the Input Strobe Setup Delay, Input Strobe Hold Delay Constraint, Output Strobe Setup Delay Constraint, and Output Strobe Hold Delay Constraint for both dut_INPUT and dut_OUTPUT module to 0 initially to eliminate unnecessary interface constraints. The phylite_interface_constraints.tcl script then automatically calculates the TcoMax and TcoMin values for input interface delay constraints and Tsu and Th values for output interface delay constraints.
The TimeQuest Analyzer generates a report based on the calculations performed by the script.
Input Interface Delay Constraints
Use the TcoMax value to calculate the Input Strobe Setup Delay Constraint and TcoMin value to calculate the Input Strobe Hold Delay Constraint. The input interface delay constraints must include board skew to perform accurate timing analysis.
Input Strobe Setup Delay Constraint = TcoMax + board skew
Input Strobe Hold Delay Constraint = TcoMin + board skew
Update the new Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values to the dut_INPUT module and re-compile the design.
Output Interface Delay Constraints
Use the Tsu value to calcuate the Output Strobe Setup Delay Constraint and Th value to calculate Output Strobe Hold Delay Constraint. The output interface delay constraints must include board skew to perform accurate timing analysis.
Output Strobe Setup Delay Constraint = Tsu + board skew
Output Strobe Hold Delay Constraint = Th - board skew
Update the new Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint values to the dut_OUTPUT module and re-compile the design.
|May 2017||2017.05.08||Rebranded as Intel.|
|December 2016||2016.12.09||Initial release.|