The Intel® High Level Synthesis Compiler Release Notes provide late-breaking information about the Intel® High Level Synthesis Compiler included with Intel® Quartus® Prime Design Suite Version 18.0.
- Starting with
Quartus® Prime Version 18.0, the features and devices supported by the
Intel® HLS Compiler depend on what edition
Quartus® Prime you have.
Intel® HLS Compiler publications now use icons to indicate content
and features that apply only to a specific edition as follows:
- Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Pro Edition.
- Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Standard Edition.
Compilations that target Intel® Stratix® 10 devices (-march=Stratix10) now take advantage of the following Intel® Stratix® 10 specific compiler optimizations and reporting:
- Fast Loop Orchestration
- HyperFlex Control Optimizations
- Reset Minimization
Intel® HLS Compiler now includes templated
libraries to help speed the development of your component by providing you
with FPGA-optimized code for some commonly used code. The following
Intel® HLS Compiler libraries were added in
- Random Number Generator Library
- Matrix Multiplication Library
Added new stream interface declarations:
Use this declaration when your stream packets have more than one data symbol per clock cycle. This declaration indicates the number of symbols at the end of a packet cycle that do not represent valid data.
Use this declaration to indicate if the data symbols in your stream are in big endian order or little endian order. The default is little endian order.
- Added the following new tutorials:
Renamed tutorials to reflect the renamed
Quartus® Prime components:
- usability/qsys_2xclock is now usability/platform_designer_2xclock
- usability/qsys_stitching is now usability/platform_designer_stitching
For detailed instructions about installing Intel® Quartus® Prime software, including system requirements, prerequisites, and licensing requirements, see Intel® FPGA Software Installation and Licensing .
The Intel® HLS Compiler requires the following additional software:
Mentor Graphics® ModelSim® Software
- ModelSim® - Intel® FPGA Edition
- ModelSim® - Intel® FPGA Starter Edition
On Linux systems, ModelSim® software requires the Red Hat development tools packages. Additionally, any 32-bit versions of ModelSim® software (including those provided with Intel® Quartus® Prime) require additional 32-bit libraries. The commands to install these requirements are provided in Installing the Intel® HLS Compiler on Linux Systems.
For information about all the ModelSim® software versions that the Intel® software supports, refer to the EDA Interface Information section in the Software and Device Support Release Notes for your edition of Intel® Quartus® Prime
This section provides information about known issues that affect the Intel® High Level Synthesis Compiler Version 18.0.
(Windows only) Compiling a design in a directory with a long path name can result in compile failures.
|Compile the design in a directory with a short path name.|
|(Windows only) A long path for your Intel® Quartus® Prime installation directory can prevent you from successfully compiling and running the Intel® HLS Compiler tutorials and example designs.||Move the tutorials and examples to a short path name before trying to run them.|
|(Windows only) Pragmas used in templated code are not recognized.||Manually specialize the templated code.|
|(Windows only) C++ libraries are not supported.||Use C libraries where possible. For example, use printf instead of cout.|
|(Windows only) When you compile your component, the compiler might
issue the following
warning LNK4088: image being generated due to /FORCE option; image may not run
|Ignore this warning. The executable is expected to work correctly.|
|Document Version||Intel® Quartus® Prime Version||Changes|