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AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 Devices
AN-728 | 2017.03.15
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel Arria 10 Devices
You can use
Intel®
Arria® 10 devices to implement
phase-locked loop (PLL) reconfiguration and dynamic phase shift for I/O PLLs.
Arria® 10 I/O PLL supports dynamic reconfiguration when the device is in user mode. With the dynamic reconfiguration feature, you can reconfigure I/O PLL settings in real time. You can change the divide settings of the PLL counters and the PLL bandwidth settings (loop filter setting and charge pump setting) through an Avalon® Memory-Mapped ( Avalon® -MM) interface in the Altera PLL Reconfig IP core, without the need to reconfigure the entire FPGA. Arria® 10 I/O PLL uses divide counters (N, M, and C counters) and a voltage-controlled oscillator (VCO) to synthesize the desired phase and frequency output.
You can perform dynamic reconfiguration using one of the following methods:
- Memory Initialization File (.mif) streaming reconfiguration
- Allows I/O PLL reconfiguration using predefined settings saved in an on-chip ROM. You can store many unique PLL configurations in a single ROM.
- The .mif file is generated automatically by the Altera IOPLL IP core. Using the generated .mif file during .mif streaming reconfiguration ensures the legality of the new configuration.
- Intel recommends using this reconfiguration method.
- Reconfiguration of individual PLL settings
- Supports N, M, and C counters reconfiguration.
- Supports bandwidth setting changes of the loop filter configuration. You must reconfigure the charge pump current setting and loop filter resistance setting for stable operation of the PLL if the M counter value is changed.
- Supports both read and write operations.
- This method of reconfiguration is for advanced users. You must ensure the reconfigured PLL settings are within the legal range.
With the dynamic phase shift feature of the I/O PLL, you can modify the phase of the PLL output clocks in real time. You can adjust the phase in increments of 1/8 of the VCO period.
You can perform dynamic phase shift using one of the following methods:
- Direct access to the dynamic phase shift ports in the Altera IOPLL IP core
- Supports both shift up and shift down operations.
- Supports up to seven phase shift steps in a single operation.
- Dynamic phase shift via the Altera PLL Reconfig IP core
- Available via .mif streaming reconfiguration or via reconfiguration of individual PLL settings.
- Supports only write operation.
Related information
Implementing I/O PLL Reconfiguration in the Altera PLL Reconfig IP Core
You can enable PLL reconfiguration circuitry for I/O PLL through the Avalon® -MM interface in the Altera PLL Reconfig IP core.
Avalon -MM Interface Ports in the Altera PLL Reconfig IP Core
| Port | Direction | Description |
|---|---|---|
| mgmt_clk | Input | Dynamic reconfiguration clock that drives the Altera PLL Reconfig IP core. This port must be connected to a valid clock source. The maximum input clock frequency is 100 MHz. This clock can be an independent clock source. |
| mgmt_reset | Input | Active high signal. Synchronous reset input to clear all the data in the Altera PLL Reconfig IP core. |
| mgmt_waitrequest | Output | This port goes high when PLL reconfiguration process started and remains high during PLL reconfiguration. After PLL reconfiguration process completed, this port goes low. |
| mgmt_read | Input | Active high signal. Asserts to indicate a read operation. |
| mgmt_write | Input | Active high signal. Asserts to indicate a write operation. |
| mgmt_readdata[31..0] | Output | Reads data from this port when mgmt_read signal is asserted. |
| mgmt_address[8..0] | Input | Specifies the address of the data bus for a read or write operation. |
| mgmt_writedata[31..0] | Input | Writes data to this port when mgmt_write signal is asserted. |
| mgmt_byteenable[3..0] | Input | Optional. Permits write operation to the Altera PLL Reconfig IP core from an Avalon® -MM interface with data bus width wider than 32 bits. |
| reconfig_from_pll[63..0] | Input | Bus that connects to reconfig_from_pll[63..0] bus in the Altera IOPLL IP core. |
| reconfig_to_pll[63..0] | Output | Bus that connects to reconfig_to_pll[63..0] bus in the Altera IOPLL IP core. |
Connecting the Altera IOPLL and Altera PLL Reconfig IP Cores
To connect the Altera IOPLL and Altera PLL Reconfig IP cores in your design, follow these steps:
- Connect the reconfig_to_pll[63..0] bus on the Altera PLL Reconfig IP core to the reconfig_to_pll[63..0] bus on the Altera IOPLL IP core.
- Connect the reconfig_from_pll[63..0] bus on the Altera PLL Reconfig IP core to the reconfig_from_pll[63..0] bus on the Altera IOPLL IP core.
- Connect the mgmt_clk port to a valid clock source.
- Connect the mgmt_reset port, mgmt_waitrequest port, mgmt_read port, mgmt_write port, mgmt_readdata[31..0] bus, and mgmt_writedata[31..0] bus to user control logic to perform read and write operations.
Connectivity between the Altera IOPLL and Altera PLL Reconfig IP Cores
Figure 1. Connectivity between the Altera IOPLL and Altera PLL Reconfig IP Cores in the
Quartus® Prime Software
I/O PLL Reconfiguration Write Operation
To perform a write operation for I/O PLL reconfiguration in the Altera PLL Reconfig IP core, follow these steps:
- Set the address bus value for mgmt_address, and the data bus value for mgmt_writedata. To enable write operation for I/O PLL reconfiguration, assert the mgmt_write signal for one mgmt_clk cycle.
- Repeat step 1 to set the values for up to eight sets of address bus and data bus.
- Set the start address (9’b000000000) for mgmt_address, and any value for mgmt_writedata. To start the write operation for I/O PLL reconfiguration, assert the mgmt_write signal for one mgmt_clk cycle.
- After the write operation is complete, the mgmt_waitrequest signal is de-asserted.
Each dynamic reconfiguration command (address-data pair) can be of one of the three types:
- Counter setting reconfiguration
- Bandwidth setting reconfiguration
- Dynamic phase shift
You can issue up to eight dynamic reconfiguration commands before triggering reconfiguration by writing to the start address. Issuing more than eight commands causes the internal reconfiguration FIFO to overflow.
Write Operation for .mif Streaming Reconfiguration
The dynamic reconfiguration commands can also be stored in a .mif file for .mif streaming reconfiguration. To enable .mif streaming in the Altera PLL Reconfig IP core, select the appropriate checkbox in the parameter editor and provide the path to the .mif file before generating your IP core.
To perform .mif streaming reconfiguration, follow these steps:
- Set the start .mif address (9'b000010000) for mgmt_address and the base address within the ROM for mgmt_writedata. To start the .mif streaming operation of I/O PLL reconfiguration, assert the mgmt_write signal for one mgmt_clk cycle.
- After the reconfiguration is complete, the mgmt_waitrequest signal is de-asserted.
You should not write to the start address
(9'b0) in the .mif file.
I/O PLL Reconfiguration Read Operation
To perform a read operation for I/O PLL reconfiguration in the Altera PLL Reconfig IP core, follow these steps:
- Set the address bus value for mgmt_address. To enable and start the read operation for I/O PLL reconfiguration, assert mgmt_read for one mgmt_clk cycle.
- After the read operation is complete, the mgmt_waitrequest signal is de-asserted. At the same time, read the data available from mgmt_readdata port.
With I/O PLL reconfiguration read
operation, you can read the current I/O PLL settings. This operation is only supported
for counter settings and bandwidth settings. Each read operation retrieves data from a
single address.
An I/O PLL reconfiguration read operation requires at least three mgmt_clk cycles of latency.
Address Bus and Data Bus Settings
Assign a value of “0” for all the unused bits in the address bus and the data bus during write and read operations.
Address Bus and Data Bus Setting for Counter Setting Reconfiguration
| Counter Name | Address Bus Bit Setting (Binary) | Data bus bit setting (Binary) |
|---|---|---|
| M | 9’b010010000 |
|
| N | 9’b010100000 | |
| C0 | 9’b011000000 | |
| C1 | 9’b011000001 | |
| C2 | 9’b011000010 | |
| C3 | 9’b011000011 | |
| C4 | 9’b011000100 | |
| C5 | 9’b011000101 | |
| C6 | 9’b011000110 | |
| C7 | 9’b011000111 | |
| C8 | 9’b011001000 |
Address Bus and Data Bus Setting for Dynamic Phase Shift
| Counter Name | Address Bus Bit Setting (Binary) | Data Bus Bit Setting (Binary) |
|---|---|---|
| C0 | 9’b100000000 |
|
| C1 | 9’b100000001 | |
| C2 | 9’b100000010 | |
| C3 | 9’b100000011 | |
| C4 | 9’b100000100 | |
| C5 | 9’b100000101 | |
| C6 | 9’b100000110 | |
| C7 | 9’b100000111 | |
| C8 | 9’b100001000 | |
| All C counters | 9’b100001111 |
Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration
| Bandwidth Component | Address Bus Bit Setting (Binary) | Data Bus Bit Setting (Binary) |
|---|---|---|
| Loop filter setting | 9’b001000000 | Data[9..6] |
| Charge pump setting | 9’b000100000 | Data[5..0] |
Data Bus Setting for Loop Filter and Charge Pump Settings
| M Counter Total Division Value | Low Bandwidth | Medium Bandwidth | High Bandwidth | |||
|---|---|---|---|---|---|---|
| Loop Filter Setting | Charge Pump Setting | Loop Filter Setting | Charge Pump Setting | Loop Filter Setting | Charge Pump Setting | |
| Data[9..6] | Data[5..0] | Data[9..6] | Data[5..0] | Data[9..6] | Data[5..0] | |
| 4–5 | 4’b0010 | 6’b001011 | 4’b0010 | 6’b011000 | 4’b0010 | 6’b001100 |
| 6–7 | 4’b0011 | 6’b010000 | 4’b0011 | 6’b001011 | 4’b0011 | 6’b011000 |
| 8–15 | 4’b0011 | 6’b010000 | 4’b0011 | 6’b011000 | 4’b0011 | 6’b100000 |
| 16–23 | 4’b0011 | 6’b001011 | 4’b0011 | 6’b001100 | 4’b0011 | 6’b001101 |
| 24–43 | 4’b0100 | 6’b010000 | 4’b0100 | 6’b011000 | 4’b0100 | 6’b100000 |
| 44–64 | 4’b0101 | 6’b010000 | 4’b0101 | 6’b011000 | 4’b0101 | 6’b100000 |
| 64–124 | 4’b0101 | 6’b011000 | 4’b0101 | 6’b100000 | 4’b0101 | 6’b101000 |
| >125 | 4’b0110 | 6’b011000 | 4’b0110 | 6’b100000 | 4’b0110 | 6’b101000 |
Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
| Address Bus Bit Setting (Binary) | Data Bus Bit Setting (Binary) |
|---|---|
| 9’b000010000 |
Data[8..0] .mif base address in ROM that is desired to use for I/O PLL reconfiguration. |
.mif Streaming Reconfiguration
The .mif file stores the commands as ROM in M20K embedded memory block. You can send these commands to the Altera PLL Reconfig IP core via .mif streaming reconfiguration.
Each .mif streaming reconfiguration must be indicated with the Start of .mif (SOM) and End of .mif (EOM) operation codes.
The .mif streaming reconfiguration starts at the .mif base address that you specify. The Altera PLL Reconfig IP core reads the .mif file contents until it encounters a SOM operation code (Opcode). From this point, the .mif streaming reconfiguration simulates the commands that the user logic could send to the Altera PLL Reconfig IP core. These commands are address-data pairs in the .mif file specifying the setting to be reconfigured to the new value. The address is stored as an Opcode in the lower nine bits of each entry word, while data is stored in the lower 18 bits of each entry word. The bit settings for address-data pairs in the .mif file is the same as the address bus and data bus bit setting for counter setting reconfiguration and bandwidth setting reconfiguration. The .mif streaming reconfiguration ends when the EOM Opcode is encountered.
You can save multiple I/O PLL configurations in a .mif file if you mark the SOM and EOM Opcodes appropriately. The Altera PLL Reconfig IP core reads the setting from ROM in M20K embedded memory block, which has default address width = 9 bits and data width = 32 bits with total of 512 words. These sizes can change as parameters are passed to the top-level module. For .mif streaming reconfiguration, data width must be 32 bits to match the Altera PLL Reconfig IP core.
Intel recommends using a .mif file generated from the Altera IOPLL IP core with the desired reconfiguration setting. The generated .mif file stores the entire I/O PLL profile.
.mif File Format
Figure 2. Single .mif File Format for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration Operation Codes
| Operation Name | Operation Code | Description |
|---|---|---|
| Start of .mif (SOM) | 9’b000011110 | Indicates start of I/O PLL reconfiguration. |
| End of .mif (EOM) | 9’b000011111 | Indicates end of I/O PLL reconfiguration. |
Implementing I/O PLL Dynamic Phase Shift in the Altera IOPLL IP Core
You can use the Altera IOPLL IP core to perform phase shifting directly through the dynamic phase shift ports.
Dynamic Phase Shift Ports in the Altera IOPLL IP Core
Figure 3. Dynamic Phase Shift Port Ports in the Altera IOPLL IP Core
| Port | Direction | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| scanclk | Input | Dynamic phase shift clock that drives the Altera IOPLL IP core dynamic phase shift operation. This port must be connected to a valid clock source. The maximum input clock frequency is 100 MHz. | ||||||||||||||||||||||
| phase_en | Input | Active high signal. Asserts to start the dynamic phase shift operation. | ||||||||||||||||||||||
| updn | Input | Determines the direction of dynamic phase shift. When updn = 0, phase shift is in negative direction (shift down). When updn = 1, phase shift is in positive direction (shift up). | ||||||||||||||||||||||
| cntsel[4..0] | Input |
Determines the counter to be selected to perform dynamic phase shift operation.
|
||||||||||||||||||||||
| num_phase_shift[2..0] | Input | Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period. | ||||||||||||||||||||||
| phase_done | Output | The Altera IOPLL IP core drives this port high for one scanclk cycle after dynamic phase shift operation is complete. |
I/O PLL Dynamic Phase Shift Operation
To perform dynamic phase shift operation for an I/O PLL in the Altera IOPLL IP core, follow these steps:
- Set the value for updn, cntsel[4..0], and num_phase_shift[2..0] ports.
- Assert phase_en port for at least two scanclk cycles.
Each phase_en pulse indicates one dynamic phase shift operation. The phase_done output goes low to indicate that dynamic phase shift is in progress. You can only assert the phase_en signal after the phase_done signal goes from low to high.
The updn, cntsel[4..0], and num_phase_shift[2..0] ports are synchronous to the scanclk cycle.
When the phase_done signal transitions from high to low, the phase_done signal is synchronous to the rising edge of the scanclk signal. The transition from low to high is asynchronous to the scanclk signal.
Depending on the VCO and scanclk frequency, the low time of the phase_done signal may be greater than or less than one scanclk cycle.
Design Considerations
Resetting the PLL
- When changing the M counter, N counter, or loop filter settings, the I/O PLL may lose and regain lock. To maintain the appropriate phase relationship between the reference clock and output clocks, assert the areset signal to reset the PLL after reconfiguration is complete. Intel recommends always resetting the PLL after any reconfiguration operation to the M counter, N counter, or loop filter settings.
- When changing the C counter settings, you may lose the expected phase relationship between the C counters. Assert the areset signal after reconfiguration is complete to restore the expected phase relationship. Reset is not required if the phase relationships are not important to your application.
- Resetting the PLL does not modify the counter or loop filter settings. However, resetting the PLL undoes any dynamic phase shift operations that were performed. After the PLL is reset, the phase shift on the C counters is restored to the originally programmed settings.
Configuration Constraints
The I/O PLL configuration must obey the following constraints:
- The phase frequency detector (PFD) and VCO each have a legal frequency range of operation.
- The loop filter settings must be appropriate for the M counter value and user-selected bandwidth mode.
If any of these configuration constraints are violated, the I/O PLL may fail to lock or may exhibit poor jitter performance.
If you reconfigure the PLL using .mif streaming, the Altera IOPLL IP core always produce legal PLL configurations in the auto-generated .mif file.
You must ensure that the PLL settings are legal if you apply the PLL reconfiguration write operations directly. The Altera IOPLL parameter editor provides several methods to identify the legal PLL configurations and to explore the combination of legal configurations.
Timing Closure
- Reconfiguring a PLL's counter and loop filter settings changes both the output frequency and the clock uncertainty of that PLL. Dynamic phase shift only affects the output clock phase.
- The TimeQuest timing analyzer in the Quartus® Prime software performs timing analysis for the initial PLL settings only. You must verify that your design closes timing after dynamic reconfiguration or dynamic phase shift.
- Intel recommends compiling PLL designs with each intended configuration setting to determine the variation in the clock with PLL settings.
Other Design Considerations
- I/O PLL reconfiguration interface supports a free running mgmt_clk signal. I/O PLL dynamic phase shift interface supports a free running scanclk signal. These interfaces eliminate the need to precisely control the start and stop of mgmt_clk and scanclk signals.
- Reconfiguration commands are queued in the Altera PLL Reconfiguation IP core, and removed after they are complete. Assert a high pulse on the mgmt_reset signal to reset the IP core to its initial state, clearing any queued commands.
- Use caution when reconfiguring a PLL with a non-zero phase shift setting. Modifying the M counter or N counter settings does not change the relative phase shift (in percent), but alters the absolute phase shift (in picoseconds). Modifying the C counter settings does not change the absolute phase shift, but modifies the relative phase shift.
- When writing to the Altera PLL Reconfig IP core using a Nios® processor's Avalon® -MM master, use the default Nios® word-addressing scheme. The Nios® processor produces an 11-bit address. Qsys automatically converts this 11-bit address into the appropriate 9-bit address as required by the Altera PLL Reconfig IP core.
Related information
Using the Design Examples
You must install the Intel Quartus® Prime software version 15.0 or later. The software must be installed on a Windows® or Linux® computer that meets the Quartus® Prime software minimum requirements.
Design Example 1: I/O PLL Reconfiguration
The design example uses a 10AX115R2F40I2SGE2 device to demonstrate the implementation of the I/O PLL dynamic reconfiguration using the Altera PLL Reconfig IP core. This design example consists of the Altera IOPLL IP core, Altera PLL Reconfig IP core and Altera In-System Sources & Probe IP core.
The I/O PLL synthesizes two output clocks of 400 MHz with 0 ps phase shift and 200 MHz with 0 ps phase shift on counter C0 output and counter C1 output respectively at medium bandwidth. The input reference clock is 50 MHz.
The Altera PLL Reconfig IP core connects to a state machine to perform I/O PLL reconfiguration operation. A low pulse on the reset_SM input through the Altera In-System Sources & Probe IP core triggers the I/O PLL reconfiguration operation. After I/O PLL reconfiguration operation has completed, the I/O PLL operates in the following configuration at medium bandwidth:
- 100 MHz with 0 ps phase shift on counter C0 output
- 100 MHz with 312 ps phase shift on counter C1 output
To run the test with the design example, perform these steps:
- Download and restore the an728-iopll-reconfig-general.qar file.
- If necessary, change the device and pin assignments (refclk, c0_out, c1_out, and locked pins) of the design example to match your hardware.
- Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
- Open the AN.spf and program the device with test.sof.
- Assert a high pulse on reset_reconfig signal to reset the Altera PLL Reconfig IP core. Then assert a high pulse on reset_SM signal to start the I/O PLL dynamic reconfiguration operation.
Figure 4. Waveform Example for I/O PLL Reconfiguration Design
Example
Design Example 2: .mif Streaming Reconfiguration
This design example is similar to Design Example 1, except that the dynamic reconfiguration commands (address-data pair) are stored in the AN.mif file.
To run this design example, follow the steps in Design Example 1, except Step 1. Download and restore the an728-iopll-reconfig-mif-streaming.qar file for this design example.
Figure 5. Waveform Example for .mif Streaming Reconfiguration Design Example
Related tasks
Design Example 3: I/O PLL Dynamic Phase Shift
This design example uses the same device and pin assignments as in Design Example 1 and Design Example 2. This design example demonstrates the implementation of the I/O PLL dynamic phase shift in the Altera IOPLL IP core.
The I/O PLL synthesizes two output clocks of 200 MHz with 0 ps phase shift on counter C0 output and counter C1 output at medium bandwidth. The input reference clock is 50 MHz.
The dynamic phase shift ports of the Altera IOPLL IP core connect to a state machine to perform I/O PLL dynamic phase shift operation. A low pulse on the reset_SM input through the Altera In-System Sources & Probe IP core triggers the I/O PLL dynamic phase shift operation. After I/O PLL dynamic phase shift operation has completed, counter C1 is phase shifted 208 ps for one positive phase shift step.
To run the test with the design example, perform these steps:
- Download and restore the an728-iopll-dynamic_phase_shift.qar file.
- If necessary, change the device and pin assignments (refclk, c0_out, c1_out, and locked pins) of the design example to match your hardware.
- Recompile the design example. Ensure that the design example does not contain any timing violation after recompilation.
- Open the AN.spf and program the device with test.sof.
- Assert a high pulse on reset_SM signal to start the I/O PLL dynamic phase shift operation.
Figure 6. Waveform Example for I/O PLL Dynamic Phase Shift Design Example
Document Revision History
| Date | Version | Changes |
|---|---|---|
| March 2017 | 2017.03.15 | Rebranded as Intel. |
| May 2016 | 2016.05.05 |
|
| June 2015 | 2015.06.12 |
|
| January 2015 | 2015.01.23 | Initial release. |