The D-PHY provides a synchronous connection between a master and slave. The minimum PHY configuration consists of a clock and one or more data signals. The D-PHY uses two wires per data lane and two wires for the clock lane. The lane can operate in a high-speed (HS) signaling mode for fast-data traffic and low-power (LP) signaling mode for control purpose.
The maximum data rate that can be supported in high-speed signaling is determined by the performance of the transmitter, receiver, and interconnect implementations. In practice, the typical implementation has a bit rate of approximately 500-800 Mbps per lane in high-speed mode for passive D-PHY. However, for some D-PHY applications, the bit rate can go up to 1.5 Gbps per lane. The maximum data rate in low-power mode is 10 Mbps.
The three possible implementations for connecting MIPI / D-PHY compliant device to Intel FPGAs are as follows:
- Use of an external D-PHY ASSP (for example Meticom MC2000x and MC2090x devices) as an active level shifter
- Use passive resistor network to create the compatible D-PHY with FPGA general-purpose I/O (GPIO)
- Use FPGA transceiver I/O to achieve higher data rate
This application note discusses the implementation using passive resistor network to achieve the lowest cost implementation.
The D-PHY can support bidirectional data transmission or unidirectional data transmission. CSI-2 protocol only requires unidirectional data transmission. Thus this implementation of a MIPI D-PHY compatible solution for Intel’s low cost FPGAs only supports unidirectional data transmission.
- Receiving interface—FPGA I/O receives the high-speed or low-power signaling from a MIPI D-PHY transmitter (TX) device such as camera sensor or imager
- Transmitting interface—FPGA I/O transmits the high-speed or low-power signaling to a MIPI D-PHY receiver (RX) device such as a host or display
The high-speed differential signaling and low-power single-ended serial signals have different electrical characteristics. This application note covers the recommendation of the I/O standard for the FPGA I/O to emulate a MIPI D-PHY RX or TX, and provide an electrically compatibility between FPGA I/O and the MIPI interface. The single-ended mode uses LVCMOS or HSTL I/O standard for low-power mode, and differential I/O standard (LVDS) for high-speed mode. Resistors are used to connect, isolate, terminate, and level set to construct the compatible D-PHY.
MIPI D-PHY IP incorporated in the FPGA is able to receive and transmit serial data which consists of one clock and one or more data lanes. The data lanes can switch between the high-speed and low-power signaling through a passive resistor network in unidirectional mode as shown in the following figures. This may be a spate IP block or integrated into the MIPI CSI-2 protocol controllers depending on the IP source or third-party IP partner. The lane control and interface logic are essential to the D-PHY functionality that needs to be built inside the FPGA logic.
This figure shows high-speed and low-power modes in a single lane and common resistor configuration.
When the interface is in high-speed mode, the MIPI D-PHY RX device presents a 100 Ω differential termination. When the common-mode of the lines indicates that the interface is in low-power mode, the 100 Ω termination is switched to high Z.
|Device||FPGA I/O Buffer Mode||Signaling Mode||I/O Standard||I/O Voltage Supply (V)|
|Cyclone® IV GX, Cyclone® V, Intel® MAX® 10||RX||High-speed||LVDS 1||2.5 2||—|
|Low-power||HSTL-12 1, 1.2 V LVCMOS||2.5 2, 1.2||—|
|TX||High-speed||Differential HSTL-18 3||—||1.8|
|Low-power||1.8 V LVCMOS 3, 2.5 V LVCMOS||—||1.8, 2.5|
|VCMRX(DC)||Common-mode voltage high-speed receive mode||70||—||330||mV|
|VIDTH||Differential input high threshold||—||—||70||mV|
|VIDTL||Differential input low threshold||–70||—||—||mV|
|VIHHS||Single-ended input high voltage||—||—||460||mV|
|VILHS||Single-ended input low voltage||–40||—||—||mV|
|VTERM-EN||Single-ended threshold for high-speed termination enable||—||—||450||mV|
|ZID||Differential input impedance||80||100||125||Ω|
|VIH||Logic 1 input voltage||880||—||—||mV|
|VIL||Logic 0 input voltage, not in ultra low power (ULP) state||—||—||550||mV|
|VCMTX||High-speed transmit static common-mode voltage 4||150||200||250||mV|
||ΔVCMTX(1,0)|||VCMTX mismatch when output is Differential-1 or Differential-0 5||—||—||5||mV|
||VOD|||High-speed transmit differential voltage 4||140||200||270||mV|
||ΔVOD|||VOD mismatch when output is Differential-1 or Differential-0 5||—||—||10||mV|
|VOHHS||High-speed output high voltage 4||—||—||360||mV|
|ZOS||Single-ended output impedance||40||50||62.5||Ω|
|ΔZOS||Single-ended output impedance mismatch||—||—||10||%|
|VOH||Thevenin output high level||1.1||1.2||1.3||V|
|VOL||Thevenin output low level||–50||—||50||mV|
The DC specifications for 1.2 V LVCMOS, HSTL-12, and LVDS I/O standards are as stipulated in the device datasheets for the respective devices. When an FPGA functions as a MIPI D-PHY receiver, the transmitted high-speed and low-power signals from the MIPI D-PHY transmitter are expected to meet these FPGA I/O standards specifications with passive resistor network.
|I/O Standard||VCCIO (V)||VIL (V)||VIH (V)|
|1.2 V||1.14||1.2||1.26||–0.3||0.35 × VCCIO||0.65 × VCCIO||VCCIO + 0.3|
|I/O Standard||VCCIO (V)||VREF (V)||VTT (V)|
|HSTL-12 Class I, II||1.14||1.2||1.26||0.48 × VCCIO 6||0.50 × VCCIO 6||0.52 × VCCIO 6||—||0.50 × VCCIO||—|
|0.47 × VCCIO 7||0.50 × VCCIO 7||0.53 × VCCIO 7|
|I/O Standard||VIL(DC) (V)||VIH(DC) (V)||VIL(AC) (V)||VIH(AC) (V)|
|HSTL-12 Class I, II||–0.15||VREF – 0.08||VREF + 0.08||VCCIO + 0.15||–0.24||VREF – 0.15||VREF + 0.15||VCCIO + 0.24|
|I/O Standard||VCCIO (V)||VID (V)||VICM (V)|
|LVDS||2.375||2.5||2.625||100||—||0.05||DMAX ≤ 500 Mbps||1.8|
|0.55||500 Mbps ≤ DMAX ≤ 700 Mbps||1.8|
|1.05||DMAX > 700 Mbps||1.55|
The DC specifications for Differential HSTL-18, 1.8 V LVCMOS, and 2.5 V LVCMOS I/O standards are as stipulated in the device datasheets for the respective devices. When an FPGA functions as a MIPI D-PHY transmitter, the transmitted high-speed and low-power signals from the FPGA I/O are expected to meet the high-speed and low-power MIPI D-PHY receiver specifications with passive resistor network.
|I/O Standard||VCCIO (V)||VOL (V)||VOH (V)|
|HSTL-188 Class I, II||1.71||1.8||1.89||0.4||VCCIO – 0.4|
|1.8 V LVCMOS||1.71||1.8||1.89||0.45||VCCIO – 0.45|
|2.5 V LVCMOS||2.375||2.5||2.625||0.4||2|
IBIS simulation using HyperLynx is performed to show the link simulation between the MIPI D-PHY, transmission line, passive resistor network, and FPGA I/O for Cyclone® IV, Cyclone® V, and Intel® Intel® MAX® 10 devices. The simulation demonstrates the following signaling modes with the passive resistor networks setups:
- Input and output differential and common-mode voltage levels for high-speed signaling
- Single-ended input and output high and low voltage levels for low-power signaling
During normal operation, either high-speed or low-power signaling can drive a lane. The states for high-speed lane are Differential-0 and Differential-1. The two single-ended lines in low-power lane states can drive a different or same state depending on the mode of operation. The low-power lane can drive four possible states: LP00, LP11, LP01 and LP10.
The high-speed mode is simulated at 840 Mbps for Cyclone® IV and Cyclone® V devices, and 720 Mbps for Intel® MAX® 10 device. The low-power mode is simulated at 10 Mbps for Cyclone® IV, Cyclone® V, and Intel® MAX® 10 devices. The simulation uses simple transmission line that assumed to have the characteristics impedance of 50 Ω with 500 ps transmission delay.
In the HS-RX and LP-RX mode simulation, the FPGA acts as a receiver to receive the MIPI D-PHY high-speed and low-power signals from MIPI D-PHY TX device in a single lane. The differential termination is fixed at 300 Ω across the LVDS pair in a single lane. The termination is set high to avoid the complexity of switching in and out of the high-speed mode termination. The termination supports the required signal quality at the targeted data rates although the termination does not match the characteristics impedance of the transmission line. The 300 Ω load between the lines minimizes loading in the low-power mode and in the LP01 or LP10 state. The two fixed series termination resistors are used for the low-power signals.
The simulated waveforms for the Cyclone® IV, Cyclone® V, and Intel® MAX® 10 devices are based on the recommended setup. The I/O standards used in the FPGA I/O pins are compliant to the following voltage levels transmitted from the MIPI D-PHY TX device under typical conditions:
- High-speed signals—Output differential (VOD) and common mode (VOCM) voltage levels
- Low-power single-ended signals—Output voltage high (VOH) and output voltage low(VOL) signals
In the HS-TX and LP-TX mode simulation, the FPGA acts as a MIPI D-PHY TX device. The MIPI D-PHY RX device is represented by the package parasitic components with a worst case capacitive load of 3.0 pF.
When the interface is in high-speed mode, the MIPI D-PHY RX device presents a 100 Ω differential termination in this simulation (as shown in the FPGA As Transmitter HS-TX Mode IBIS Simulation Circuit diagram). When the common-mode of the lines indicates that the interface is in low-power mode, the 100 Ω termination is switched to high Z, which is not shown in the LP-TX mode IBIS simulation circuit (as shown in the FPGA As Transmitter LP-TX Mode IBIS Simulation Circuit diagram). In this simulation, the MIPI D-PHY high-speed receiver is turned off during the low-power mode operation, thus the input differential termination is removed.
The IBIS simulation uses the buffers in different modes as follows:
- High-speed mode
- A differential buffer is used to transmit signals.
- Two single-ended buffers are configured as input mode to act as tri-stated outputs.
- Low-power mode
- A differential buffer is configured as input mode to act as tri-stated output.
- Two single-ended buffers are used to transmit signals.
The simulated waveforms for the Cyclone® IV, Cyclone® V, and Intel® MAX® 10 devices are based on the recommended setup.
The I/O standards used in the FPGA I/O pins are compliant to the following voltage levels as defined for high-speed or low-power MIPI D-PHY RX device under typical conditions:
- High-speed signals—Input differential (VID) and common mode (VICM) voltage levels
- Low-power single-ended signals—Input voltage high (VIH) and input voltage low (VIL) signals
The signal quality for high-speed signal is better with less jitter compared to the high-speed signal when FPGA acts as the receiving interface. The 100 Ω differential termination resistor at the load provides good impedance matching to the characteristic impedance of the transmission line.
The interconnect between the MIPI TX and RX devices must be designed with caution. The interconnect includes PCB traces, connectors (if any), and cable media (typically flex-foils).
Signal quality guidelines are as follows:
- Match the electrical length of all pairs as close as possible to maximize data valid margins.
- Place the passive components as close as possible to the FPGA. Avoid any stub when placing the passive resistors on the high-speed signal trace. Minimize the stub length from the low-power signal trace to high-speed signal trace.
- Use the on chip termination feature on FPGA I/O whenever possible.
- The reference characteristics impedance level per line is 100 Ω for differential and 50 Ω for single-ended. Control the impedance of the trace on the PCB to avoid impedance mismatch between the driver output impedance and input impedance of the receiver over the operating frequency.
- Keep the traces matched in lengths and as short as possible. The flight time for signals across the interconnect should not exceed 2 ns.
- Ensure equal length for all high-speed differential traces. The differential channel is also used for low-power single-ended signaling. Intel recommends applying only very loosely coupled differential transmission lines.
- If probe points are required, ensure they are in line with the trace and not creating a transmission line stub.
- Do not place noisy signals (example: voltage regulator module, clock generator) over or near MIPI signals.
- Use the I/O standards supported for the FPGA I/O as listed in the I/O standards for MIPI D-PHY Implementation table.
The passive resistor network in this application illustrates and validates the IBIS simulations. You can use the passive resistor network to build a FPGA I/O based compatible MIPI D-PHY for receiving or transmitting both high-speed and low-power signals using various FPGA GPIO connected. The passive resistor network is capable to enable an electrically compatible connection between Intel FPGA I/O to a MIPI D-PHY TX or RX device via MIPI D-PHY interface.
|FPGA Implementation||Passive Resistor Value (Ω)|
|FPGA unidirectional receiver implementation||300||100||—||—||—|
|FPGA unidirectional transmitter implementation||—||—||150||60||100|
|Device||Supported Data Rate (Mbps)|
|Cyclone® IV, Cyclone® V||840|
|Intel® MAX® 10||720|
Intel recommends performing HSPICE/IBIS simulations to verify the signal quality based on your specific system setup and PCB info at the desired operating frequency.
Actual achievable frequency depends on design- and system-specific factors. Perform HSPICE/IBIS simulation based on your specific design, system setup, and PCB info to determine the maximum achievable frequency.
The MIPI D-PHY passive solution with different approaches (I/O, passive network, and FPGA devices) are validated using multiple demo boards. You can use the following demo boards as reference:
- Intel 10M50 Evaluation Kit, EK-10M50F484 (available March 2016 onwards)
- Internal HSMC Passive D-PHY lab validation board for use with Cyclone® V Development Kits
- Arrow DECA Intel® MAX® 10 Evaluation Kit
For more information about the demo boards, contact your local Intel sales representatives.
|November 2017||2017.11.20||Updated links.|
|May 2017||2017.05.08||Rebranded as Intel.|
|December 2015||2015.12.23||Initial release.|